jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
287 lines
9.8 KiB
VHDL
287 lines
9.8 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: dlx-rtl.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:54:44 $
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--
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--------------------------------------------------------------------------
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--
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-- Register transfer level architecture of DLX processor.
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--
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use std.textio.all,
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work.images.image_hex,
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work.bv_arithmetic.all,
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work.dlx_instr.all,
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work.alu_types.all;
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architecture rtl of dlx is
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component alu
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port (s1 : in dlx_word;
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s2 : in dlx_word;
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result : out dlx_word;
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latch_en : in bit;
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func : in alu_func;
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zero, negative, overflow : out bit);
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end component;
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component reg_file
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port (a1 : in dlx_reg_addr; -- port1 address
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q1 : out dlx_word; -- port1 read data
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a2 : in dlx_reg_addr; -- port2 address
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q2 : out dlx_word; -- port2 read data
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a3 : in dlx_reg_addr; -- port3 address
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d3 : in dlx_word; -- port3 write data
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write_en : in bit); -- port3 write enable
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end component;
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component latch
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port (d : in dlx_word;
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q : out dlx_word;
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latch_en : in bit);
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end component;
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component reg_1_out
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port (d : in dlx_word;
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q : out dlx_word_bus bus;
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latch_en : in bit;
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out_en : in bit);
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end component;
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component reg_2_out
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port (d : in dlx_word;
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q1, q2 : out dlx_word_bus bus;
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latch_en : in bit;
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out_en1, out_en2 : in bit);
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end component;
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component reg_3_out
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port (d : in dlx_word;
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q1, q2, q3 : out dlx_word_bus bus;
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latch_en : in bit;
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out_en1, out_en2, out_en3 : in bit);
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end component;
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component reg_2_1_out
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port (d : in dlx_word;
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q1, q2 : out dlx_word_bus bus;
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q3 : out dlx_word;
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latch_en : in bit;
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out_en1, out_en2 : in bit);
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end component;
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component mux2
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port (i0, i1 : in dlx_word;
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y : out dlx_word;
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sel : in bit);
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end component;
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component ir
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port (d : in dlx_word; -- instruction input from memory
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immed_q1, immed_q2 : out dlx_word_bus bus;
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ir_out : out dlx_word; -- instruction output to control
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latch_en : in bit;
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immed_sel1, immed_sel2 : in immed_size; -- select 16-bit or 26-bit immed
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immed_unsigned1, immed_unsigned2 : in bit; -- extend immed unsigned/signed
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immed_en1, immed_en2 : in bit); -- enable immed const outputs
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end component;
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component controller
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port (phi1, phi2 : in bit;
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reset : in bit;
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halt : out bit;
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width : out mem_width;
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write_enable : out bit;
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mem_enable : out bit;
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ifetch : out bit;
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ready : in bit;
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alu_latch_en : out bit;
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alu_function : out alu_func;
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alu_zero, alu_negative, alu_overflow : in bit;
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reg_s1_addr, reg_s2_addr, reg_dest_addr : out dlx_reg_addr;
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reg_write : out bit;
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c_latch_en : out bit;
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a_latch_en, a_out_en : out bit;
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b_latch_en, b_out_en : out bit;
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temp_latch_en, temp_out_en1, temp_out_en2 : out bit;
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iar_latch_en, iar_out_en1, iar_out_en2 : out bit;
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pc_latch_en, pc_out_en1, pc_out_en2 : out bit;
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mar_latch_en, mar_out_en1, mar_out_en2 : out bit;
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mem_addr_mux_sel : out bit;
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mdr_latch_en, mdr_out_en1, mdr_out_en2, mdr_out_en3 : out bit;
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mdr_mux_sel : out bit;
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ir_latch_en : out bit;
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ir_immed_sel1, ir_immed_sel2 : out immed_size;
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ir_immed_unsigned1, ir_immed_unsigned2 : out bit;
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ir_immed_en1, ir_immed_en2 : out bit;
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current_instruction : in dlx_word;
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const1, const2 : out dlx_word_bus bus);
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end component;
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signal s1_bus, s2_bus : dlx_word_bus;
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signal dest_bus : dlx_word;
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signal alu_latch_en : bit;
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signal alu_function : alu_func;
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signal alu_zero, alu_negative, alu_overflow : bit;
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signal reg_s1_addr, reg_s2_addr, reg_dest_addr : dlx_reg_addr;
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signal reg_file_out1, reg_file_out2, reg_file_in : dlx_word;
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signal reg_write : bit;
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signal a_out_en, a_latch_en : bit;
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signal b_out_en, b_latch_en : bit;
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signal c_latch_en : bit;
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signal temp_out_en1, temp_out_en2, temp_latch_en : bit;
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signal iar_out_en1, iar_out_en2, iar_latch_en : bit;
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signal pc_out_en1, pc_out_en2, pc_latch_en : bit;
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signal pc_to_mem : dlx_word;
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signal mar_out_en1, mar_out_en2, mar_latch_en : bit;
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signal mar_to_mem : dlx_word;
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signal mem_addr_mux_sel : bit;
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signal mdr_out_en1, mdr_out_en2, mdr_out_en3, mdr_latch_en : bit;
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signal mdr_in : dlx_word;
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signal mdr_mux_sel : bit;
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signal current_instruction : dlx_word;
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signal ir_latch_en : bit;
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signal ir_immed_sel1, ir_immed_sel2 : immed_size;
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signal ir_immed_unsigned1, ir_immed_unsigned2 : bit;
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signal ir_immed_en1, ir_immed_en2 : bit;
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begin
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the_alu : alu
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port map (s1 => s1_bus, s2 => s2_bus, result => dest_bus,
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latch_en => alu_latch_en, func => alu_function,
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zero => alu_zero, negative => alu_negative, overflow => alu_overflow);
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the_reg_file : reg_file
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port map (a1 => reg_s1_addr, q1 => reg_file_out1,
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a2 => reg_s2_addr, q2 => reg_file_out2,
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a3 => reg_dest_addr, d3 => reg_file_in,
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write_en => reg_write);
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c_reg : latch
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port map (d => dest_bus, q => reg_file_in, latch_en => c_latch_en);
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a_reg : reg_1_out
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port map (d => reg_file_out1, q => s1_bus,
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latch_en => a_latch_en, out_en => a_out_en);
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b_reg : reg_1_out
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port map (d => reg_file_out2, q => s2_bus,
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latch_en => b_latch_en, out_en => b_out_en);
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temp_reg : reg_2_out
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port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
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latch_en => temp_latch_en,
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out_en1 => temp_out_en1, out_en2 => temp_out_en2);
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iar_reg : reg_2_out
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port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus,
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latch_en => iar_latch_en,
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out_en1 => iar_out_en1, out_en2 => iar_out_en2);
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pc_reg : reg_2_1_out
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port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => pc_to_mem,
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latch_en => pc_latch_en,
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out_en1 => pc_out_en1, out_en2 => pc_out_en2);
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mar_reg : reg_2_1_out
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port map (d => dest_bus, q1 => s1_bus, q2 => s2_bus, q3 => mar_to_mem,
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latch_en => mar_latch_en,
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out_en1 => mar_out_en1, out_en2 => mar_out_en2);
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mem_addr_mux : mux2
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port map (i0 => pc_to_mem, i1 => mar_to_mem, y => a,
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sel => mem_addr_mux_sel);
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mdr_reg : reg_3_out
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port map (d => mdr_in, q1 => s1_bus, q2 => s2_bus, q3 => d,
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latch_en => mdr_latch_en,
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out_en1 => mdr_out_en1, out_en2 => mdr_out_en2,
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out_en3 => mdr_out_en3);
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mdr_mux : mux2
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port map (i0 => dest_bus, i1 => d, y => mdr_in,
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sel => mdr_mux_sel);
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instr_reg : ir
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port map (d => d, immed_q1 => s1_bus, immed_q2 => s2_bus,
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ir_out => current_instruction,
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latch_en => ir_latch_en,
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immed_sel1 => ir_immed_sel1, immed_sel2 => ir_immed_sel2,
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immed_unsigned1 => ir_immed_unsigned1,
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immed_unsigned2 => ir_immed_unsigned2,
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immed_en1 => ir_immed_en1, immed_en2 => ir_immed_en2);
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the_controller : controller
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port map (phi1, phi2, reset, halt,
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width, write_enable, mem_enable, ifetch, ready,
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alu_latch_en, alu_function, alu_zero, alu_negative, alu_overflow,
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reg_s1_addr, reg_s2_addr, reg_dest_addr, reg_write,
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c_latch_en, a_latch_en, a_out_en, b_latch_en, b_out_en,
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temp_latch_en, temp_out_en1, temp_out_en2,
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iar_latch_en, iar_out_en1, iar_out_en2,
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pc_latch_en, pc_out_en1, pc_out_en2,
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mar_latch_en, mar_out_en1, mar_out_en2, mem_addr_mux_sel,
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mdr_latch_en, mdr_out_en1, mdr_out_en2,
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mdr_out_en3, mdr_mux_sel,
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ir_latch_en, ir_immed_sel1, ir_immed_sel2,
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ir_immed_unsigned1, ir_immed_unsigned2, ir_immed_en1, ir_immed_en2,
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current_instruction, s1_bus, s2_bus);
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debug_s1 : if debug generate
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s1_monitor : process (s1_bus)
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variable L : line;
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begin
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write(L, tag);
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write(L, string'(" s1_monitor: "));
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write(L, image_hex(s1_bus));
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writeline(output, L);
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end process s1_monitor;
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end generate;
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debug_s2 : if debug generate
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s2_monitor : process (s2_bus)
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variable L : line;
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begin
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write(L, tag);
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write(L, string'(" s2_monitor: "));
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write(L, image_hex(s2_bus));
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writeline(output, L);
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end process s2_monitor;
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end generate;
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debug_dest : if debug generate
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dest_monitor : process (dest_bus)
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variable L : line;
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begin
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write(L, tag);
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write(L, string'(" dest_monitor: "));
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write(L, image_hex(dest_bus));
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writeline(output, L);
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end process dest_monitor;
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end generate;
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end rtl;
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