212 lines
11 KiB
VHDL
212 lines
11 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Dual-ported register file with asynchrous read
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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-- $Header: /tmp/cvsroot/VHDL/lib/misc/dpram_2w2r_virtex4.vhd,v 1.1 2008-08-23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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library UNISIM;
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use UNISIM.vcomponents.all;
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entity dpram_2w2r is
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Generic
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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Port
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(
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clk_a : in STD_LOGIC;
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clk_b : in STD_LOGIC;
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en_a : in STD_LOGIC;
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en_b : in STD_LOGIC;
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we_a : in STD_LOGIC;
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we_b : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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din_b : in unsigned (data_width-1 downto 0);
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dout_a : out unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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end dpram_2w2r;
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architecture Structure of dpram_2w2r is
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signal do_a : std_logic_vector(31 downto 0);
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signal do_b : std_logic_vector(31 downto 0);
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signal di_a : std_logic_vector(31 downto 0);
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signal di_b : std_logic_vector(31 downto 0);
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signal ad_a : std_logic_vector(14 downto 0);
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signal ad_b : std_logic_vector(14 downto 0);
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signal wr_a : std_logic_vector(3 downto 0);
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signal wr_b : std_logic_vector(3 downto 0);
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begin
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-- RAMB16: 16k+2k Parity Paramatizable block RAM
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-- Virtex-4
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-- Xilinx HDL Libraries Guide, version 9.1i
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RAMB16_inst : RAMB16
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generic map
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(
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DOA_REG => 0, -- Optional output registers on the A port (0 or 1)
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DOB_REG => 0, -- Optional output registers on the B port (0 or 1)
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INIT_A => X"000000000", -- Initial values on A output port
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INIT_B => X"000000000", -- Initial values on B output port
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INVERT_CLK_DOA_REG => FALSE, -- Invert clock on A port output registers (TRUE or FALSE)
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INVERT_CLK_DOB_REG => FALSE, -- Invert clock on B port output registers (TRUE or FALSE)
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RAM_EXTENSION_A => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
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RAM_EXTENSION_B => "NONE", -- "UPPER", "LOWER" or "NONE" when cascaded
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READ_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
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READ_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
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SIM_COLLISION_CHECK => "ALL", -- Collision check enable "ALL", "WARNING_ONLY",
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-- "GENERATE_X_ONLY" or "NONE"
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SRVAL_A => X"000000000", -- Port A output value upon SSR assertion
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SRVAL_B => X"000000000", -- Port B output value upon SSR assertion
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WRITE_MODE_A => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
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WRITE_MODE_B => "READ_FIRST", -- WRITE_FIRST, READ_FIRST or NO_CHANGE
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WRITE_WIDTH_A => 9, -- Valid values are 1,2,4,9,18 or 36
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WRITE_WIDTH_B => 9, -- Valid values are 1,2,4,9,18 or 36
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-- The following INIT_xx declarations specify the initial contents of the RAM
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INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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-- The next set of INITP_xx are for the parity bits
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INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000"
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)
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port map
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(
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CASCADEOUTA => open, -- 1-bit cascade output
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CASCADEOUTB => open, -- 1-bit cascade output
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DOA => do_a, -- 32-bit A port Data Output
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DOB => do_b, -- 32-bit B port Data Output
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DOPA => open, -- 4-bit A port Parity Output
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DOPB => open, -- 4-bit B port Parity Output
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ADDRA => ad_a, -- 15-bit A Port Address Input
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ADDRB => ad_b, -- 15-bit B Port Address Input
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CASCADEINA => '0', -- 1-bit cascade A input
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CASCADEINB => '0', -- 1-bit cascade B input
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CLKA => clk_a, -- Port A Clock
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CLKB => clk_b, -- Port B Clock
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DIA => di_a, -- 32-bit A port Data Input
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DIB => di_b, -- 32-bit B port Data Input
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DIPA => "0000", -- 4-bit A port parity Input
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DIPB => "0000", -- 4-bit B port parity Input
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ENA => en_a, -- 1-bit A port Enable Input
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ENB => en_b, -- 1-bit B port Enable Input
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REGCEA => '0', -- 1-bit A port register enable input
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REGCEB => '0', -- 1-bit B port register enable input
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SSRA => '0', -- 1-bit A port Synchronous Set/Reset Input
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SSRB => '0', -- 1-bit B port Synchronous Set/Reset Input
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WEA => wr_a, -- 4-bit A port Write Enable Input
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WEB => wr_b -- 4-bit B port Write Enable Input
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);
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-- End of RAMB16_inst instantiation
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dout_a <= unsigned(do_a(7 downto 0));
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dout_b <= unsigned(do_b(7 downto 0));
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di_a <= X"000000" & std_logic_vector(din_a);
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di_b <= X"000000" & std_logic_vector(din_b);
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ad_a <= '0' & std_logic_vector(addr_a) & "000";
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ad_b <= '0' & std_logic_vector(addr_b) & "000";
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wr_a <= (3 downto 0 => we_a);
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wr_b <= (3 downto 0 => we_b);
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end Structure;
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