jens
47e7daee7d
- fixed problems after fixed_pkg update: explicit set round and saturation mode in Cordic and CIC git-svn-id: http://moon:8086/svn/vhdl/trunk@1325 cc03376c-175c-47c8-b038-4cd826a8556b
93 lines
2.7 KiB
VHDL
93 lines
2.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 12:16:14 10/02/05
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-- Design Name:
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-- Module Name: cordic_stage - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.MATH_REAL.ALL;
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USE ieee.numeric_std.ALL;
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library ieee_proposed;
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use ieee_proposed.fixed_float_types.all;
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use ieee_proposed.fixed_pkg.all;
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library work;
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use work.fixed_util_pkg.all;
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use work.nco_pkg.all;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity waverom_dual is
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Generic
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(
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nbits_wave : integer := 12;
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nbits_wave_frac : integer := 12;
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nbits_rom_depth : integer := 12
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);
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Port
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(
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clk : in std_logic;
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addr_i : in unsigned(nbits_rom_depth-1 downto 0);
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addr_q : in unsigned(nbits_rom_depth-1 downto 0);
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wave_i_out : out sfixed;
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wave_q_out : out sfixed
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);
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end waverom_dual;
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architecture Behavioral of waverom_dual is
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-------------------------------------------------------------------------------
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constant rom_depth : integer := 2**nbits_rom_depth;
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type wave_mem_t is array (0 to rom_depth-1) of sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low);
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constant sfixed_proto : sfixed(sproto(nbits_wave, nbits_wave_frac)'high downto sproto(nbits_wave, nbits_wave_frac)'low) := (others => '0');
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-------------------------------------------------------------------------------
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function to_wave_mem(wave_real : real_array_t; len : integer; proto : sfixed) return wave_mem_t is
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variable res : wave_mem_t;
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begin
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for i in 0 to len-1 loop
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res(i) := to_sfixed(wave_real(i), proto, fixed_saturate, fixed_round);
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end loop;
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return res;
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end to_wave_mem;
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-------------------------------------------------------------------------------
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-- Create ROM
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constant real_wave_tbl : real_array_t(0 to rom_depth-1) := cos_tbl(rom_depth, 0.25/real(rom_depth), 0.0);
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constant wave_tbl : wave_mem_t := to_wave_mem(real_wave_tbl, rom_depth, sfixed_proto);
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-------------------------------------------------------------------------------
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begin
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-------------------------------------------------------------------------------
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proc_wave: process(clk)
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begin
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if rising_edge(clk) then
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wave_i_out <= wave_tbl(to_integer(addr_i));
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wave_q_out <= wave_tbl(to_integer(addr_q));
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end if;
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end process;
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------------------------------------------------------------
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end Behavioral;
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