jens
cd4b4bb99a
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@902 cc03376c-175c-47c8-b038-4cd826a8556b
65 lines
1.6 KiB
VHDL
65 lines
1.6 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use std.textio.all; -- Imports the standard textio package.
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use work.utils_pkg.all; -- Imports the standard textio package.
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ENTITY crc32 IS
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Generic
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(
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crc32_init : unsigned(31 downto 0) := X"00000000"
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);
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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din_vld : in STD_LOGIC;
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din : in unsigned(7 downto 0);
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crc32_vld : out STD_LOGIC;
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crc32_out : out unsigned(31 downto 0)
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);
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END crc32;
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ARCHITECTURE behavior OF crc32 IS
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type crc_table_t is array (0 to 15) of unsigned(31 downto 0);
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constant crc_table : crc_table_t :=
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(
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X"4DBDF21C", X"500AE278", X"76D3D2D4", X"6B64C2B0",
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X"3B61B38C", X"26D6A3E8", X"000F9344", X"1DB88320",
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X"A005713C", X"BDB26158", X"9B6B51F4", X"86DC4190",
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X"D6D930AC", X"CB6E20C8", X"EDB71064", X"F0000000"
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);
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signal crc0 : unsigned(31 downto 0);
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signal crc1 : unsigned(31 downto 0);
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signal crc2 : unsigned(31 downto 0);
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--------------------------------------------------------------------------
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begin
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crc1 <= X"0" & crc0(31 downto 4) xor crc_table(to_integer(crc0(3 downto 0) xor din(3 downto 0)));
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crc2 <= X"0" & crc1(31 downto 4) xor crc_table(to_integer(crc1(3 downto 0) xor din(7 downto 4)));
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crc32_out <= crc0;
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--------------------------------------------------------------------------
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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crc0 <= crc32_init;
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crc32_vld <= '0';
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elsif din_vld = '1' then
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crc0 <= crc2;
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crc32_vld <= '1';
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end if;
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end if;
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end process;
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--------------------------------------------------------------------------
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end behavior;
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