jens/vhdl
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
Files
6147fe66e367a6dc307b88095d5b7cffb66ff7a5
vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.twr
T
jens e27c0f791a update 
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@782 cc03376c-175c-47c8-b038-4cd826a8556b
2010-03-13 10:50:30 +00:00

1178 lines
86 KiB
Plaintext
Raw Blame History

--------------------------------------------------------------------------------
Release 10.1.03 Trace (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
C:\Programme\Xilinx101\ISE\bin\nt\unwrapped\trce.exe -ise
W:/vhdl/projects/mips_sys/ise101/mips_sys/mips_sys.ise -intstyle ise -v 3 -s 10
-xml mips_sys mips_sys.ncd -o mips_sys.twr mips_sys.pcf -ucf
W:/vhdl/projects/mips_sys/ise101/mips_sys/ucf/systest.ucf
Design file: mips_sys.ncd
Physical constraint file: mips_sys.pcf
Device,package,speed: xc4vsx35,ff668,-10 (PRODUCTION 1.68 2008-07-25, STEPPING level ES)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
================================================================================
Timing constraint: NET "sys_ac97_bit_clk_IBUF1" PERIOD = 80 ns HIGH 50%;
3447 paths analyzed, 643 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 6.700ns.
--------------------------------------------------------------------------------
Slack: 36.650ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 (FF)
Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11 (FF)
Requirement: 40.000ns
Data Path Delay: 3.345ns (Levels of Logic = 0)
Clock Path Skew: -0.005ns (2.621 - 2.626)
Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns
Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X33Y79.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11>
inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_11
SLICE_X58Y78.BY net (fanout=14) 2.779 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<11>
SLICE_X58Y78.CLK Tdick 0.280 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_11
------------------------------------------------- ---------------------------
Total 3.345ns (0.566ns logic, 2.779ns route)
(16.9% logic, 83.1% route)
--------------------------------------------------------------------------------
Slack: 37.046ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 (FF)
Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15 (FF)
Requirement: 40.000ns
Data Path Delay: 2.678ns (Levels of Logic = 0)
Clock Path Skew: -0.276ns (2.456 - 2.732)
Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns
Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15 to inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X27Y85.YQ Tcko 0.286 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15>
inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_15
SLICE_X47Y78.BY net (fanout=13) 2.100 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<15>
SLICE_X47Y78.CLK Tdick 0.292 inst_ac97_wb/inst_ac_io/inst_ac_in/tag<15>
inst_ac97_wb/inst_ac_io/inst_ac_in/tag_15
------------------------------------------------- ---------------------------
Total 2.678ns (0.578ns logic, 2.100ns route)
(21.6% logic, 78.4% route)
--------------------------------------------------------------------------------
Slack: 37.336ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 (FF)
Destination: inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10 (FF)
Requirement: 40.000ns
Data Path Delay: 2.643ns (Levels of Logic = 0)
Clock Path Skew: -0.021ns (2.621 - 2.642)
Source Clock: sys_ac97_bit_clk_IBUF falling at 40.000ns
Destination Clock: sys_ac97_bit_clk_IBUF rising at 80.000ns
Clock Uncertainty: 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10 to inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X32Y89.YQ Tcko 0.307 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10>
inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg_10
SLICE_X58Y78.BX net (fanout=13) 2.057 inst_ac97_wb/inst_ac_io/inst_ac_in/rx_reg<10>
SLICE_X58Y78.CLK Tdick 0.279 inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
inst_ac97_wb/inst_ac_io/inst_ac_in/data_array_1_10
------------------------------------------------- ---------------------------
Total 2.643ns (0.586ns logic, 2.057ns route)
(22.2% logic, 77.8% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_clk = PERIOD TIMEGRP "sys_clk" 9.9 ns HIGH 50%;
450849 paths analyzed, 11154 endpoints analyzed, 9 failing endpoints
9 timing errors detected. (9 setup errors, 0 hold errors)
Minimum period is 10.193ns.
--------------------------------------------------------------------------------
Slack: -0.293ns (requirement - (data path - clock path skew + uncertainty))
Source: arb_gnt_0 (FF)
Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F (RAM)
Requirement: 9.900ns
Data Path Delay: 10.084ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 9.900ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0>
arb_gnt_0
SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0>
SLICE_X38Y63.Y Tilo 0.195 N739
Mmux_ADDR_O241
SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30>
SLICE_X40Y59.XMUX Tbxx 0.513 N105
CYC_O1_SW1
SLICE_X40Y61.G4 net (fanout=2) 0.416 N105
SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb
CYC_I_ac971
SLICE_X38Y67.G4 net (fanout=15) 0.917 CYC_I_ac971
SLICE_X38Y67.Y Tilo 0.195 MDAT_I<8>27
CYC_I_gpio1
SLICE_X36Y60.G3 net (fanout=27) 0.668 CYC_I_gpio
SLICE_X36Y60.Y Tilo 0.195 N54
MDAT_I<2>56_SW0_SW0
SLICE_X47Y59.G4 net (fanout=1) 0.949 N135
SLICE_X47Y59.Y Tilo 0.194 MDAT_I<2>56
MDAT_I<2>56_SW0
SLICE_X47Y59.F4 net (fanout=1) 0.159 N1197
SLICE_X47Y59.X Tilo 0.194 MDAT_I<2>56
MDAT_I<2>56
SLICE_X44Y57.G4 net (fanout=1) 0.384 MDAT_I<2>56
SLICE_X44Y57.Y Tilo 0.195 MDAT_I<2>
MDAT_I<2>89_SW0
SLICE_X44Y57.F3 net (fanout=1) 0.213 N1324
SLICE_X44Y57.X Tilo 0.195 MDAT_I<2>
MDAT_I<2>89
SLICE_X34Y53.BY net (fanout=1) 0.774 MDAT_I<2>
SLICE_X34Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<2>
inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM3.SLICEM_F
------------------------------------------------- ---------------------------
Total 10.084ns (3.493ns logic, 6.591ns route)
(34.6% logic, 65.4% route)
--------------------------------------------------------------------------------
Slack: -0.194ns (requirement - (data path - clock path skew + uncertainty))
Source: arb_gnt_0 (FF)
Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM)
Requirement: 9.900ns
Data Path Delay: 9.985ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 9.900ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0>
arb_gnt_0
SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0>
SLICE_X38Y63.Y Tilo 0.195 N739
Mmux_ADDR_O241
SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30>
SLICE_X40Y59.XMUX Tbxx 0.513 N105
CYC_O1_SW1
SLICE_X40Y61.G4 net (fanout=2) 0.416 N105
SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb
CYC_I_ac971
SLICE_X38Y67.G4 net (fanout=15) 0.917 CYC_I_ac971
SLICE_X38Y67.Y Tilo 0.195 MDAT_I<8>27
CYC_I_gpio1
SLICE_X42Y64.G3 net (fanout=27) 0.918 CYC_I_gpio
SLICE_X42Y64.Y Tilo 0.195 N851
MDAT_I<0>56_SW0_SW0
SLICE_X45Y64.G4 net (fanout=1) 0.322 N143
SLICE_X45Y64.Y Tilo 0.194 MDAT_I<0>56
MDAT_I<0>56_SW0
SLICE_X45Y64.F3 net (fanout=1) 0.222 N1205
SLICE_X45Y64.X Tilo 0.194 MDAT_I<0>56
MDAT_I<0>56
SLICE_X40Y53.G2 net (fanout=1) 0.757 MDAT_I<0>56
SLICE_X40Y53.Y Tilo 0.195 MDAT_I<0>
MDAT_I<0>89_SW0
SLICE_X40Y53.F3 net (fanout=1) 0.213 N1332
SLICE_X40Y53.X Tilo 0.195 MDAT_I<0>
MDAT_I<0>89
SLICE_X38Y53.BY net (fanout=1) 0.616 MDAT_I<0>
SLICE_X38Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0>
inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
------------------------------------------------- ---------------------------
Total 9.985ns (3.493ns logic, 6.492ns route)
(35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
Slack: -0.174ns (requirement - (data path - clock path skew + uncertainty))
Source: arb_gnt_0 (FF)
Destination: inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F (RAM)
Requirement: 9.900ns
Data Path Delay: 9.965ns (Levels of Logic = 10)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 9.900ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: arb_gnt_0 to inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X40Y64.XQ Tcko 0.360 arb_gnt<0>
arb_gnt_0
SLICE_X38Y63.G2 net (fanout=117) 1.138 arb_gnt<0>
SLICE_X38Y63.Y Tilo 0.195 N739
Mmux_ADDR_O241
SLICE_X40Y59.BX net (fanout=8) 0.973 ADDR_O<30>
SLICE_X40Y59.XMUX Tbxx 0.513 N105
CYC_O1_SW1
SLICE_X40Y61.G4 net (fanout=2) 0.416 N105
SLICE_X40Y61.Y Tilo 0.195 CYC_I_usb
CYC_I_ac971
SLICE_X39Y61.G4 net (fanout=15) 0.719 CYC_I_ac971
SLICE_X39Y61.Y Tilo 0.194 N1207
CYC_I_ac972
SLICE_X42Y64.G2 net (fanout=58) 1.097 CYC_I_ac97
SLICE_X42Y64.Y Tilo 0.195 N851
MDAT_I<0>56_SW0_SW0
SLICE_X45Y64.G4 net (fanout=1) 0.322 N143
SLICE_X45Y64.Y Tilo 0.194 MDAT_I<0>56
MDAT_I<0>56_SW0
SLICE_X45Y64.F3 net (fanout=1) 0.222 N1205
SLICE_X45Y64.X Tilo 0.194 MDAT_I<0>56
MDAT_I<0>56
SLICE_X40Y53.G2 net (fanout=1) 0.757 MDAT_I<0>56
SLICE_X40Y53.Y Tilo 0.195 MDAT_I<0>
MDAT_I<0>89_SW0
SLICE_X40Y53.F3 net (fanout=1) 0.213 N1332
SLICE_X40Y53.X Tilo 0.195 MDAT_I<0>
MDAT_I<0>89
SLICE_X38Y53.BY net (fanout=1) 0.616 MDAT_I<0>
SLICE_X38Y53.CLK Tds 1.062 inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/_varindex0000<0>
inst_mips_top/inst_biu/inst_bin_fifo/inst_dpram_1w1r/Mram_RAM1.SLICEM_F
------------------------------------------------- ---------------------------
Total 9.965ns (3.492ns logic, 6.473ns route)
(35.0% logic, 65.0% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_sdram_clk = PERIOD TIMEGRP "sdram_clk" 7.5 ns HIGH 50%;
1524 paths analyzed, 435 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 7.330ns.
--------------------------------------------------------------------------------
Slack: 0.170ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty (FF)
Requirement: 7.500ns
Data Path Delay: 7.206ns (Levels of Logic = 6)
Clock Path Skew: 0.000ns
Source Clock: sdram_clk0 rising at 0.000ns
Destination Clock: sdram_clk0 rising at 7.500ns
Clock Uncertainty: 0.124ns
Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y18.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
SLICE_X14Y155.G1 net (fanout=15) 1.217 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26>
SLICE_X14Y155.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0
SLICE_X16Y156.G2 net (fanout=6) 0.794 N318
SLICE_X16Y156.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<3>
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc
SLICE_X17Y155.G1 net (fanout=7) 0.595 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/rinc
SLICE_X17Y155.XMUX Tif5x 0.574 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<5>
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>1
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<5>_f5
SLICE_X16Y157.F3 net (fanout=3) 0.464 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/gnxt_r<5>
SLICE_X16Y157.X Tilo 0.195 N1006
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677_SW0
SLICE_X17Y156.G3 net (fanout=1) 0.226 N1006
SLICE_X17Y156.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677
SLICE_X17Y156.F3 net (fanout=1) 0.222 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty677/O
SLICE_X17Y156.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/fifo_pre_empty6100
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_fifo_async_ctrl/empty
------------------------------------------------- ---------------------------
Total 7.206ns (3.688ns logic, 3.518ns route)
(51.2% logic, 48.8% route)
--------------------------------------------------------------------------------
Slack: 0.180ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 (FF)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5 (FF)
Requirement: 3.750ns
Data Path Delay: 3.446ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: sdram_clk0 rising at 0.000ns
Destination Clock: sdram_clk0 falling at 3.750ns
Clock Uncertainty: 0.124ns
Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X6Y167.XQ Tcko 0.360 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
SLICE_X6Y171.G3 net (fanout=9) 0.927 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_0_BRB1
SLICE_X6Y171.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/sdr_addr_5_mux00041
OLOGIC_X0Y187.D1 net (fanout=1) 1.337 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.addr_5
OLOGIC_X0Y187.CLK Todck 0.627 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr<5>
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_addr_5
------------------------------------------------- ---------------------------
Total 3.446ns (1.182ns logic, 2.264ns route)
(34.3% logic, 65.7% route)
--------------------------------------------------------------------------------
Slack: 0.190ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM (RAM)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3 (FF)
Requirement: 7.500ns
Data Path Delay: 7.186ns (Levels of Logic = 5)
Clock Path Skew: 0.000ns
Source Clock: sdram_clk0 rising at 0.000ns
Destination Clock: sdram_clk0 rising at 7.500ns
Clock Uncertainty: 0.124ns
Clock Uncertainty: 0.124ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
RAMB16_X1Y18.DOB26 Trcko_DORB 2.100 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sd_cmd_fifo/inst_dpram_1w1r/Mram_RAM
SLICE_X14Y155.G1 net (fanout=15) 1.217 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cmd_fifo_dout<26>
SLICE_X14Y155.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/Mcount_cycle_cnt_eqn_112
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6_SW0
SLICE_X13Y158.G2 net (fanout=6) 0.745 N318
SLICE_X13Y158.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd4-In6
SLICE_X13Y158.F3 net (fanout=2) 0.228 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/N24
SLICE_X13Y158.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en1
SLICE_X13Y161.G2 net (fanout=6) 0.562 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cc_load_en
SLICE_X13Y161.Y Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001_SW0
SLICE_X13Y161.F4 net (fanout=2) 0.168 N316
SLICE_X13Y161.X Tilo 0.194 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
SLICE_X15Y160.CE net (fanout=4) 0.642 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_not0001
SLICE_X15Y160.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt<3>
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/cycle_cnt_3
------------------------------------------------- ---------------------------
Total 7.186ns (3.624ns logic, 3.562ns route)
(50.4% logic, 49.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_unrelate_SDRAM_path" TIG;
24 paths analyzed, 22 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Delay: 9.594ns (data path - clock path skew + uncertainty)
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF)
Data Path Delay: 3.036ns (Levels of Logic = 1)
Clock Path Skew: -6.314ns (-2.401 - 3.913)
Source Clock: CLK_O rising
Destination Clock: sdram_clk0 rising
Clock Uncertainty: 0.244ns
Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.120ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y176.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
SLICE_X4Y154.G1 net (fanout=20) 1.519 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
SLICE_X4Y154.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141
SLICE_X5Y154.CE net (fanout=1) 0.429 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke
SLICE_X5Y154.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
------------------------------------------------- ---------------------------
Total 3.036ns (1.088ns logic, 1.948ns route)
(35.8% logic, 64.2% route)
--------------------------------------------------------------------------------
Delay: 9.133ns (data path - clock path skew + uncertainty)
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 (FF)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8 (FF)
Data Path Delay: 2.602ns (Levels of Logic = 1)
Clock Path Skew: -6.287ns (-2.401 - 3.886)
Source Clock: CLK_O rising
Destination Clock: sdram_clk0 rising
Clock Uncertainty: 0.244ns
Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.120ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X11Y167.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
SLICE_X4Y154.G4 net (fanout=9) 1.085 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd12
SLICE_X4Y154.Y Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_ddr_phy/part_ctrl_reg.cke
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_Out141
SLICE_X5Y154.CE net (fanout=1) 0.429 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/cke
SLICE_X5Y154.CLK Tceck 0.553 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd8
------------------------------------------------- ---------------------------
Total 2.602ns (1.088ns logic, 1.514ns route)
(41.8% logic, 58.2% route)
--------------------------------------------------------------------------------
Delay: 8.894ns (data path - clock path skew + uncertainty)
Source: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 (FF)
Destination: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7 (FF)
Data Path Delay: 2.328ns (Levels of Logic = 2)
Clock Path Skew: -6.322ns (-2.409 - 3.913)
Source Clock: CLK_O rising
Destination Clock: sdram_clk0 rising
Clock Uncertainty: 0.244ns
Clock Uncertainty: 0.244ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.248ns
Phase Error (PE): 0.120ns
Maximum Data Path: inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13 to inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y176.YQ Tcko 0.340 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
SLICE_X10Y162.F2 net (fanout=20) 1.171 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_ctrl/st_ctrl_FSM_FFd13
SLICE_X10Y162.X Tilo 0.195 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
SLICE_X11Y162.F1 net (fanout=1) 0.387 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In9
SLICE_X11Y162.CLK Tfck 0.235 inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7-In62
inst_sdram_ctrl_frontend_wb/inst_sdram_ctrl/inst_sdram_cmd/st_sdr_FSM_FFd7
------------------------------------------------- ---------------------------
Total 2.328ns (0.770ns logic, 1.558ns route)
(33.1% logic, 66.9% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_vga_clk = PERIOD TIMEGRP "vga_clk" 8 ns HIGH 50%;
12615 paths analyzed, 693 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 7.614ns.
--------------------------------------------------------------------------------
Slack: 0.386ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF)
Destination: inst_vga_frontend/inst_vga_backend/Result<5>1_FRB (FF)
Requirement: 8.000ns
Data Path Delay: 7.479ns (Levels of Logic = 5)
Clock Path Skew: 0.000ns
Source Clock: vga_clk rising at 0.000ns
Destination Clock: vga_clk rising at 8.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.270ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X60Y177.YQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7
SLICE_X55Y173.F4 net (fanout=2) 1.037 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
SLICE_X55Y173.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3>
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311
SLICE_X54Y173.BX net (fanout=3) 0.154 inst_vga_frontend/inst_vga_backend/N13
SLICE_X54Y173.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/N15
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5
SLICE_X54Y171.BX net (fanout=3) 0.827 inst_vga_frontend/inst_vga_backend/N15
SLICE_X54Y171.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5
SLICE_X54Y170.G1 net (fanout=1) 0.587 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
SLICE_X54Y170.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129
SLICE_X54Y172.G1 net (fanout=2) 0.568 inst_vga_frontend/inst_vga_backend/N11
SLICE_X54Y172.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001
SLICE_X60Y179.SR net (fanout=14) 1.179 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000
SLICE_X60Y179.CLK Tsrck 1.157 inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
inst_vga_frontend/inst_vga_backend/Result<5>1_FRB
------------------------------------------------- ---------------------------
Total 7.479ns (3.127ns logic, 4.352ns route)
(41.8% logic, 58.2% route)
--------------------------------------------------------------------------------
Slack: 0.496ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 (FF)
Destination: inst_vga_frontend/inst_vga_backend/Result<4>1_FRB (FF)
Requirement: 8.000ns
Data Path Delay: 7.369ns (Levels of Logic = 5)
Clock Path Skew: 0.000ns
Source Clock: vga_clk rising at 0.000ns
Destination Clock: vga_clk rising at 8.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.270ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7 to inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X60Y177.YQ Tcko 0.360 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_7
SLICE_X55Y173.F4 net (fanout=2) 1.037 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<7>
SLICE_X55Y173.X Tilo 0.194 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count<3>
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq000311
SLICE_X54Y173.BX net (fanout=3) 0.154 inst_vga_frontend/inst_vga_backend/N13
SLICE_X54Y173.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/N15
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq00011_f5
SLICE_X54Y171.BX net (fanout=3) 0.827 inst_vga_frontend/inst_vga_backend/N15
SLICE_X54Y171.XMUX Tbxx 0.513 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111_f5
SLICE_X54Y170.G1 net (fanout=1) 0.587 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003111
SLICE_X54Y170.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_FSM_FFd3
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00003129
SLICE_X54Y172.G1 net (fanout=2) 0.568 inst_vga_frontend/inst_vga_backend/N11
SLICE_X54Y172.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/state_cmp_eq0002
inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and00001
SLICE_X59Y178.SR net (fanout=14) 1.189 inst_vga_frontend/inst_vga_backend/inst_vga_timing/inst_vga_sync_h/count_and0000
SLICE_X59Y178.CLK Tsrck 1.037 inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
inst_vga_frontend/inst_vga_backend/Result<4>1_FRB
------------------------------------------------- ---------------------------
Total 7.369ns (3.007ns logic, 4.362ns route)
(40.8% logic, 59.2% route)
--------------------------------------------------------------------------------
Slack: 0.505ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 (FF)
Destination: inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4 (RAM)
Requirement: 8.000ns
Data Path Delay: 7.156ns (Levels of Logic = 7)
Clock Path Skew: -0.204ns (2.503 - 2.707)
Source Clock: vga_clk rising at 0.000ns
Destination Clock: vga_clk rising at 8.000ns
Clock Uncertainty: 0.135ns
Clock Uncertainty: 0.135ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.270ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1 to inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X56Y157.XQ Tcko 0.360 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb_1
SLICE_X57Y156.G3 net (fanout=3) 0.633 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>
SLICE_X57Y156.COUT Topcyg 0.559 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntb<1>_rt
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
SLICE_X57Y157.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<1>
SLICE_X57Y157.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<2>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
SLICE_X57Y158.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<3>
SLICE_X57Y158.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<4>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
SLICE_X57Y159.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<5>
SLICE_X57Y159.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<6>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
SLICE_X57Y160.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<7>
SLICE_X57Y160.COUT Tbyp 0.086 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<8>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
SLICE_X57Y161.CIN net (fanout=1) 0.000 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_cy<9>
SLICE_X57Y161.XMUX Tcinx 0.438 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<11>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/Madd_nxtb_addsub0000_xor<10>
SLICE_X57Y153.G4 net (fanout=1) 0.728 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb_addsub0000<10>
SLICE_X57Y153.Y Tilo 0.194 inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/cntg<9>
inst_vga_frontend/inst_linefifo/inst_fifo_async_ctrl/inst_gray_counter_r/nxtb<10>1
RAMB16_X4Y13.ADDRB13 net (fanout=10) 3.474 inst_vga_frontend/inst_linefifo/ptr_r<10>
RAMB16_X4Y13.CLKB Trcck_ADDRB 0.426 inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
inst_vga_frontend/inst_linefifo/inst_dpram_1w1r/Mram_RAM4
------------------------------------------------- ---------------------------
Total 7.156ns (2.321ns logic, 4.835ns route)
(32.4% logic, 67.6% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: PATH "TS_unrelate_VGA_path" TIG;
64 paths analyzed, 64 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------
Delay: 6.138ns (data path - clock path skew + uncertainty)
Source: inst_vga_frontend/cg_color_2_5 (FF)
Destination: inst_vga_frontend/inst_vga_backend/vga_blue_5 (FF)
Data Path Delay: 5.597ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising
Destination Clock: vga_clk rising
Clock Uncertainty: 0.541ns
Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.347ns
Phase Error (PE): 0.367ns
Maximum Data Path: inst_vga_frontend/cg_color_2_5 to inst_vga_frontend/inst_vga_backend/vga_blue_5
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X47Y109.YQ Tcko 0.340 inst_vga_frontend/cg_color_2_4
inst_vga_frontend/cg_color_2_5
SLICE_X65Y142.G1 net (fanout=2) 2.110 inst_vga_frontend/cg_color_2_5
SLICE_X65Y142.Y Tilo 0.194 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
OLOGIC_X2Y171.REV net (fanout=1) 1.656 inst_vga_frontend/inst_vga_backend/vga_blue_mux0003<5>0
OLOGIC_X2Y171.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_blue<5>
inst_vga_frontend/inst_vga_backend/vga_blue_5
------------------------------------------------- ---------------------------
Total 5.597ns (1.831ns logic, 3.766ns route)
(32.7% logic, 67.3% route)
--------------------------------------------------------------------------------
Delay: 6.087ns (data path - clock path skew + uncertainty)
Source: inst_vga_frontend/cg_color_0_7 (FF)
Destination: inst_vga_frontend/inst_vga_backend/vga_red_7 (FF)
Data Path Delay: 5.546ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising
Destination Clock: vga_clk rising
Clock Uncertainty: 0.541ns
Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.347ns
Phase Error (PE): 0.367ns
Maximum Data Path: inst_vga_frontend/cg_color_0_7 to inst_vga_frontend/inst_vga_backend/vga_red_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X48Y107.XQ Tcko 0.360 inst_vga_frontend/cg_color_0_7
inst_vga_frontend/cg_color_0_7
SLICE_X66Y137.G2 net (fanout=2) 2.036 inst_vga_frontend/cg_color_0_7
SLICE_X66Y137.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
OLOGIC_X2Y157.REV net (fanout=1) 1.658 inst_vga_frontend/inst_vga_backend/vga_red_mux0003<7>0
OLOGIC_X2Y157.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_red<7>
inst_vga_frontend/inst_vga_backend/vga_red_7
------------------------------------------------- ---------------------------
Total 5.546ns (1.852ns logic, 3.694ns route)
(33.4% logic, 66.6% route)
--------------------------------------------------------------------------------
Delay: 6.021ns (data path - clock path skew + uncertainty)
Source: inst_vga_frontend/cg_color_1_3 (FF)
Destination: inst_vga_frontend/inst_vga_backend/vga_green_3 (FF)
Data Path Delay: 5.480ns (Levels of Logic = 1)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising
Destination Clock: vga_clk rising
Clock Uncertainty: 0.541ns
Clock Uncertainty: 0.541ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.347ns
Phase Error (PE): 0.367ns
Maximum Data Path: inst_vga_frontend/cg_color_1_3 to inst_vga_frontend/inst_vga_backend/vga_green_3
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X50Y108.YQ Tcko 0.360 inst_vga_frontend/cg_color_1_3
inst_vga_frontend/cg_color_1_3
SLICE_X66Y133.G3 net (fanout=2) 2.016 inst_vga_frontend/cg_color_1_3
SLICE_X66Y133.Y Tilo 0.195 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
OLOGIC_X2Y148.REV net (fanout=1) 1.612 inst_vga_frontend/inst_vga_backend/vga_green_mux0003<3>0
OLOGIC_X2Y148.CLK Tosrck 1.297 inst_vga_frontend/inst_vga_backend/vga_green<3>
inst_vga_frontend/inst_vga_backend/vga_green_3
------------------------------------------------- ---------------------------
Total 5.480ns (1.852ns logic, 3.628ns route)
(33.8% logic, 66.2% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TS_cpu_clk = PERIOD TIMEGRP "cpu_clk" 9.9 ns HIGH 50%;
864692 paths analyzed, 11651 endpoints analyzed, 1 failing endpoint
1 timing error detected. (1 setup error, 0 hold errors)
Minimum period is 10.294ns.
--------------------------------------------------------------------------------
Slack: -0.197ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_mips_top/inst_pipeline/bcu_op_a_2 (FF)
Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
Requirement: 4.950ns
Data Path Delay: 4.917ns (Levels of Logic = 10)
Clock Path Skew: -0.170ns (2.881 - 3.051)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk falling at 4.950ns
Clock Uncertainty: 0.060ns
Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X8Y30.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<2>
inst_mips_top/inst_pipeline/bcu_op_a_2
SLICE_X10Y30.G3 net (fanout=1) 0.816 inst_mips_top/inst_pipeline/bcu_op_a<2>
SLICE_X10Y30.COUT Topcyg 0.561 inst_mips_top/inst_pipeline/EX_stage.reg_a_17
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
SLICE_X13Y42.G4 net (fanout=2) 1.015 inst_mips_top/inst_pipeline/bcu_flags_eq
SLICE_X13Y42.Y Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take
_LC_2_0
SLICE_X13Y42.F3 net (fanout=1) 0.222 _LC_2_0
SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take
inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1
inst_mips_top/inst_pipeline/pc.branch_take_1
------------------------------------------------- ---------------------------
Total 4.917ns (2.274ns logic, 2.643ns route)
(46.2% logic, 53.8% route)
--------------------------------------------------------------------------------
Slack: -0.140ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_mips_top/inst_pipeline/bcu_op_a_2 (FF)
Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
Requirement: 4.950ns
Data Path Delay: 4.860ns (Levels of Logic = 10)
Clock Path Skew: -0.170ns (2.881 - 3.051)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk falling at 4.950ns
Clock Uncertainty: 0.060ns
Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_2 to inst_mips_top/inst_pipeline/pc.branch_take_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X8Y30.XQ Tcko 0.360 inst_mips_top/inst_pipeline/bcu_op_a<2>
inst_mips_top/inst_pipeline/bcu_op_a_2
SLICE_X10Y30.G3 net (fanout=1) 0.816 inst_mips_top/inst_pipeline/bcu_op_a<2>
SLICE_X10Y30.COUT Topcyg 0.561 inst_mips_top/inst_pipeline/EX_stage.reg_a_17
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<1>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
SLICE_X13Y39.F4 net (fanout=2) 0.836 inst_mips_top/inst_pipeline/bcu_flags_eq
SLICE_X13Y39.X Tilo 0.194 inst_mips_top/inst_pipeline/pc_branch_take_mux000240
inst_mips_top/inst_pipeline/pc_branch_take_mux000240
SLICE_X13Y42.F4 net (fanout=1) 0.344 inst_mips_top/inst_pipeline/pc_branch_take_mux000240
SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take
inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1
inst_mips_top/inst_pipeline/pc.branch_take_1
------------------------------------------------- ---------------------------
Total 4.860ns (2.274ns logic, 2.586ns route)
(46.8% logic, 53.2% route)
--------------------------------------------------------------------------------
Slack: -0.073ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_mips_top/inst_pipeline/bcu_op_a_0 (FF)
Destination: inst_mips_top/inst_pipeline/pc.branch_take_1 (FF)
Requirement: 4.950ns
Data Path Delay: 4.793ns (Levels of Logic = 10)
Clock Path Skew: -0.170ns (2.881 - 3.051)
Source Clock: cpu_clk rising at 0.000ns
Destination Clock: cpu_clk falling at 4.950ns
Clock Uncertainty: 0.060ns
Clock Uncertainty: 0.060ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.120ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_mips_top/inst_pipeline/bcu_op_a_0 to inst_mips_top/inst_pipeline/pc.branch_take_1
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X9Y30.YQ Tcko 0.340 inst_mips_top/inst_pipeline/bcu_op_b<13>
inst_mips_top/inst_pipeline/bcu_op_a_0
SLICE_X10Y30.F2 net (fanout=1) 0.697 inst_mips_top/inst_pipeline/bcu_op_a<0>
SLICE_X10Y30.COUT Topcyf 0.576 inst_mips_top/inst_pipeline/EX_stage.reg_a_17
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_lut<0>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<0>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<1>
SLICE_X10Y31.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_a<1>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<2>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<3>
SLICE_X10Y32.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/bcu_op_b<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<4>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<5>
SLICE_X10Y33.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<6>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<7>
SLICE_X10Y34.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<8>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<9>
SLICE_X10Y35.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_1
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<10>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<11>
SLICE_X10Y36.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/WB_stage.reg_wptr_0
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<12>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.CIN net (fanout=1) 0.000 inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<13>
SLICE_X10Y37.COUT Tbyp 0.089 inst_mips_top/inst_pipeline/EX_stage.reg_a_16
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<14>
inst_mips_top/inst_pipeline/inst_bcu/Mcompar_flags.eq_cmp_eq0000_cy<15>
SLICE_X13Y42.G4 net (fanout=2) 1.015 inst_mips_top/inst_pipeline/bcu_flags_eq
SLICE_X13Y42.Y Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take
_LC_2_0
SLICE_X13Y42.F3 net (fanout=1) 0.222 _LC_2_0
SLICE_X13Y42.X Tilo 0.194 inst_mips_top/inst_pipeline/pc.branch_take
inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.BY net (fanout=3) 0.590 inst_mips_top/inst_pipeline/pc_branch_take_mux0002
SLICE_X17Y41.CLK Tdick 0.342 inst_mips_top/inst_pipeline/pc.branch_take_1
inst_mips_top/inst_pipeline/pc.branch_take_1
------------------------------------------------- ---------------------------
Total 4.793ns (2.269ns logic, 2.524ns route)
(47.3% logic, 52.7% route)
--------------------------------------------------------------------------------
================================================================================
Timing constraint: TSACBITCLK = PERIOD TIMEGRP "ac97_clk" 80 ns HIGH 50%;
787 paths analyzed, 73 endpoints analyzed, 0 failing endpoints
0 timing errors detected. (0 setup errors, 0 hold errors)
Minimum period is 5.284ns.
--------------------------------------------------------------------------------
Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF)
Destination: inst_ac97_wb/inst_ac_io/cnt_7 (FF)
Requirement: 80.000ns
Data Path Delay: 5.175ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 80.000ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_7
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0>
inst_ac97_wb/inst_ac_io/cnt_0
SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0>
SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018
SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9
SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002
inst_ac97_wb/inst_ac_io/cnt_not00021
SLICE_X65Y26.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002
SLICE_X65Y26.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<6>
inst_ac97_wb/inst_ac_io/cnt_7
------------------------------------------------- ---------------------------
Total 5.175ns (1.672ns logic, 3.503ns route)
(32.3% logic, 67.7% route)
--------------------------------------------------------------------------------
Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF)
Destination: inst_ac97_wb/inst_ac_io/cnt_9 (FF)
Requirement: 80.000ns
Data Path Delay: 5.175ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 80.000ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_9
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0>
inst_ac97_wb/inst_ac_io/cnt_0
SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0>
SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018
SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9
SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002
inst_ac97_wb/inst_ac_io/cnt_not00021
SLICE_X65Y27.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002
SLICE_X65Y27.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8>
inst_ac97_wb/inst_ac_io/cnt_9
------------------------------------------------- ---------------------------
Total 5.175ns (1.672ns logic, 3.503ns route)
(32.3% logic, 67.7% route)
--------------------------------------------------------------------------------
Slack: 74.716ns (requirement - (data path - clock path skew + uncertainty))
Source: inst_ac97_wb/inst_ac_io/cnt_0 (FF)
Destination: inst_ac97_wb/inst_ac_io/cnt_8 (FF)
Requirement: 80.000ns
Data Path Delay: 5.175ns (Levels of Logic = 4)
Clock Path Skew: 0.000ns
Source Clock: CLK_O rising at 0.000ns
Destination Clock: CLK_O rising at 80.000ns
Clock Uncertainty: 0.109ns
Clock Uncertainty: 0.109ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.000ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.217ns
Phase Error (PE): 0.000ns
Maximum Data Path: inst_ac97_wb/inst_ac_io/cnt_0 to inst_ac97_wb/inst_ac_io/cnt_8
Location Delay type Delay(ns) Physical Resource
Logical Resource(s)
------------------------------------------------- -------------------
SLICE_X65Y23.XQ Tcko 0.340 inst_ac97_wb/inst_ac_io/cnt<0>
inst_ac97_wb/inst_ac_io/cnt_0
SLICE_X66Y26.G1 net (fanout=9) 0.836 inst_ac97_wb/inst_ac_io/cnt<0>
SLICE_X66Y26.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2_SW1
SLICE_X66Y26.F4 net (fanout=1) 0.159 N1018
SLICE_X66Y26.X Tilo 0.195 inst_ac97_wb/inst_ac_io/N9
inst_ac97_wb/inst_ac_io/cnt_mux0000<7>2
SLICE_X64Y27.G3 net (fanout=3) 0.427 inst_ac97_wb/inst_ac_io/N9
SLICE_X64Y27.Y Tilo 0.195 inst_ac97_wb/inst_ac_io/cnt_mux0000<8>
inst_ac97_wb/inst_ac_io/cnt_cmp_eq00001
SLICE_X57Y28.G1 net (fanout=10) 1.115 inst_ac97_wb/inst_ac_io/cnt_cmp_eq0000
SLICE_X57Y28.Y Tilo 0.194 inst_ac97_wb/inst_ac_io/cnt_not0002
inst_ac97_wb/inst_ac_io/cnt_not00021
SLICE_X65Y27.CE net (fanout=5) 0.966 inst_ac97_wb/inst_ac_io/cnt_not0002
SLICE_X65Y27.CLK Tceck 0.553 inst_ac97_wb/inst_ac_io/cnt<8>
inst_ac97_wb/inst_ac_io/cnt_8
------------------------------------------------- ---------------------------
Total 5.175ns (1.672ns logic, 3.503ns route)
(32.3% logic, 67.7% route)
--------------------------------------------------------------------------------
2 constraints not met.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Clock to Setup on destination clock sys_ac97_bit_clk
----------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
----------------+---------+---------+---------+---------+
sys_ac97_bit_clk| 6.390| 3.350| | 2.174|
----------------+---------+---------+---------+---------+
Clock to Setup on destination clock sys_clk_in
---------------+---------+---------+---------+---------+
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
sys_clk_in | 10.193| 4.880| 5.147| 3.200|
---------------+---------+---------+---------+---------+
Timing summary:
---------------
Timing errors: 10 Score: 1304
Constraints cover 1334002 paths, 0 nets, and 42582 connections
Design statistics:
Minimum period: 10.294ns{1} (Maximum frequency: 97.144MHz)
------------------------------------Footnotes-----------------------------------
1) The minimum period statistic assumes all single cycle delays.
Analysis completed Tue Mar 09 13:11:34 2010
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 349 MB
Reference in New Issue View Git Blame Copy Permalink