80 lines
2.2 KiB
VHDL
80 lines
2.2 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: The ROM file for use in your VHDL design
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.cpu_pkg.all;
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-- JASM_ROM_INSERT_HERE
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ENTITY irom IS
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Port (
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clk : in STD_LOGIC;
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ce : in STD_LOGIC;
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addr : in inst_addr_t;
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dout : out inst_t
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);
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END irom;
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ARCHITECTURE dctest OF irom IS
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type imem_rom_t is array (0 to 17) of inst_t;
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-- Assembled from dctest.jsm
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constant imem_rom : imem_rom_t :=
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(
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"110000" & X"010", -- 0x000: JMP 0x010
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"110000" & X"011", -- 0x001: JMP 0x011
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"000000" & X"000", -- 0x002:
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"000000" & X"000", -- 0x003:
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"000000" & X"000", -- 0x004:
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"000000" & X"000", -- 0x005:
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"000000" & X"000", -- 0x006:
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"000000" & X"000", -- 0x007:
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"000000" & X"000", -- 0x008:
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"000000" & X"000", -- 0x009:
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"000000" & X"000", -- 0x00A:
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"000000" & X"000", -- 0x00B:
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"000000" & X"000", -- 0x00C:
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"000000" & X"000", -- 0x00D:
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"000000" & X"000", -- 0x00E:
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"000000" & X"000", -- 0x00F:
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"110000" & X"010", -- 0x010: JMP 0x010
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"111111" & X"000" -- 0x011: RETI
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);
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begin
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PROM_READ:
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process(clk, ce)
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begin
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if rising_edge(clk) and ce = '1' then
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dout <= imem_rom(to_integer(addr));
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end if;
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end process;
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end dctest;
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