jens
026c442fce
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283 lines
6.4 KiB
VHDL
283 lines
6.4 KiB
VHDL
LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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entity j1 is
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Generic
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(
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R_STACK_SIZE : natural := 32;
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D_STACK_SIZE : natural := 32
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);
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Port
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(
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sys_clk_i : in std_logic;
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sys_rst_i : in std_logic;
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io_din : in unsigned(15 downto 0);
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io_rd : out std_logic;
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io_wr : out std_logic;
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io_addr : out unsigned(15 downto 0);
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io_dout : out unsigned(15 downto 0);
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inst_din : in unsigned(15 downto 0);
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inst_addr : out unsigned(12 downto 0);
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data_addr : out unsigned(12 downto 0);
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data_we : out std_logic;
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data_en : out std_logic;
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data_din : in unsigned(15 downto 0);
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data_dout : out unsigned(15 downto 0)
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);
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end j1;
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architecture behave of j1 is
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signal insn : unsigned(15 downto 0);
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signal immediate : unsigned(15 downto 0);
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signal ramrd : unsigned(15 downto 0);
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signal dsp : unsigned(4 downto 0); -- Data stack pointer (register)
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signal dsp2 : unsigned(4 downto 0); -- register
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signal st0 : unsigned(15 downto 0); -- Return stack pointer (register)
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signal st02 : unsigned(15 downto 0); -- register
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signal dstkW2 : std_logic; -- D stack write
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signal pc : unsigned(12 downto 0); -- register
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signal pc2 : unsigned(12 downto 0); -- register
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signal rsp : unsigned(4 downto 0); -- register
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signal rsp2 : unsigned(4 downto 0); -- register
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signal rstkW2 : std_logic; -- register
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signal rstkD2 : unsigned(15 downto 0); -- register
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signal ramWE2 : std_logic; -- RAM write enable
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signal pc_plus_1 : unsigned(15 downto 0);
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type stack_t is array (integer range <>) of unsigned(15 downto 0);
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signal dstack : stack_t(0 to D_STACK_SIZE-1); -- register
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signal rstack : stack_t(0 to R_STACK_SIZE-1); -- register
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signal st1 : unsigned(15 downto 0);
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signal rst0 : unsigned(15 downto 0);
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signal st0sel : unsigned(3 downto 0);
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signal is_alu : BOOLEAN;
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signal is_lit : BOOLEAN;
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signal dd : unsigned(1 downto 0); -- D stack delta
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signal rd : unsigned(1 downto 0); -- R stack delta
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signal stack_ram_en : std_logic; -- helper for RAM R/W
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signal stack_ram_we : std_logic; -- helper for RAM R/W
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begin
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-- LINE 25:
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pc_plus_1 <= ("000" & pc) + 1;
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-- LINE 37:
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st1 <= dstack(to_integer(dsp));
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rst0 <= rstack(to_integer(rsp));
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immediate <= '1' & insn(14 downto 0);
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-- LINE 112:
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is_alu <= (insn(15 downto 13) = "011");
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is_lit <= (insn(15) = '1');
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-- LINE 115:
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io_rd <= '1' when (is_alu and (insn(11 downto 8) = X"C")) else '0';
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io_wr <= ramWE2;
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io_addr <= st0;
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io_dout <= st1;
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ramWE2 <= '1' when (is_alu and (insn(5) = '1')) else '0';
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dstkW2 <= '1' when (is_lit or (is_alu and insn(7) = '1')) else '0';
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dd <= insn(1 downto 0);
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rd <= insn(3 downto 2);
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-- LINE 27:
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-- The D and R stacks
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proc_d_and_r_stack:
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process(sys_clk_i)
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begin
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if rising_edge(sys_clk_i) then
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if dstkW2 = '1' then
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dstack(to_integer(dsp2)) <= st0;
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end if;
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if rstkW2 = '1' then
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rstack(to_integer(rsp2)) <= rstkD2;
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end if;
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end if;
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end process;
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-- LINE 40:
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-- st0sel is the ALU operation. For branch and call the operation
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-- is T, for 0branch it is N. For ALU ops it is loaded from the instruction
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-- field.
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proc_aluop_sel:
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process(insn)
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begin
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case insn(14 downto 13) is
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when "00" => st0sel <= "0000";
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when "10" => st0sel <= "0000";
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when "01" => st0sel <= "0001";
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when "11" => st0sel <= insn(11 downto 8);
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when others => st0sel <= "XXXX";
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end case;
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end process;
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-- LINE 55:
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-- define RAMS outside this module
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insn <= inst_din;
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inst_addr <= pc2(12 downto 0);
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data_en <= not (st02(15) or st02(14));
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data_we <= ramWE2 and not (st02(15) or st02(14));
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ramrd <= data_din;
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data_dout <= st1;
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data_addr <= st02(13 downto 1);
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-- LINE 85:
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-- Compute the new value of T.
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proc_alu:
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process(insn, immediate, st0sel, st0, st1, rst0, rsp, dsp)
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begin
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if insn(15) = '1' then
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st02 <= immediate;
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else
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case st0sel is
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when "0000" => st02 <= st0;
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when "0001" => st02 <= st1;
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when "0010" => st02 <= st0 + st1;
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when "0011" => st02 <= st0 and st1;
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when "0100" => st02 <= st0 or st1;
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when "0101" => st02 <= st0 xor st1;
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when "0110" => st02 <= not st0;
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when "0111" =>
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if st1 = st0 then
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st02 <= X"FFFF";
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else
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st02 <= X"0000";
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end if;
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when "1000" =>
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if signed(st1) < signed(st0) then
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st02 <= X"FFFF";
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else
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st02 <= X"0000";
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end if;
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when "1001" => st02 <= st1 srl to_integer(st0(3 downto 0));
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when "1010" => st02 <= st0 - 1;
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when "1011" => st02 <= rst0;
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when "1100" =>
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if st0(15) = '1' or st0(14) = '1' then -- LINE 104: ????
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st02 <= io_din;
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else
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st02 <= ramrd;
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end if;
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when "1101" => st02 <= st1 sll to_integer(st0(3 downto 0));
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when "1110" => st02 <= "000" & rsp & "000" & dsp; -- LINE 106: ????
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when "1111" =>
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if st1 < st0 then
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st02 <= X"FFFF";
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else
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st02 <= X"0000";
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end if;
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when others => st02 <= "XXXXXXXXXXXXXXXX";
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end case;
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end if;
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end process;
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-- LINE 126:
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proc_stack_ctrl:
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process(is_lit, is_alu, pc2, dd, rd, insn, st0, pc_plus_1, rsp, dsp)
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begin
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if is_lit then -- literal
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dsp2 <= dsp + 1;
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rsp2 <= rsp;
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rstkW2 <= '0';
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rstkD2 <= "000" & pc2;
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elsif is_alu then
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dsp2 <= dsp + (dd(1) & dd(1) & dd(1) & dd);
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rsp2 <= rsp + (rd(1) & rd(1) & rd(1) & rd);
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rstkW2 <= insn(6);
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rstkD2 <= st0;
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else -- jump/call
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-- predicated jump is like DROP
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if insn(15 downto 13) = "001" then
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dsp2 <= dsp - 1;
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else
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dsp2 <= dsp; -- *default
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end if;
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if insn(15 downto 13) = "010" then -- call
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rsp2 <= rsp + 1;
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rstkW2 <= '1';
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rstkD2 <= pc_plus_1(14 downto 0) & '0';
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else
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rsp2 <= rsp; -- *default
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rstkW2 <= '0'; -- *default
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rstkD2 <= "000" & pc2; -- *default
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end if;
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end if;
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end process;
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-- LINE 157:
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proc_pc:
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process(sys_rst_i, is_alu, insn, pc, st0, rst0, pc_plus_1)
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begin
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if sys_rst_i = '1' then
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pc2 <= pc;
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else
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if ((insn(15 downto 13) = "000")
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or ((insn(15 downto 13) = "001")
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and (st0 = X"0000"))
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or (insn(15 downto 13) = "010")) then
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pc2 <= insn(12 downto 0);
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elsif is_alu and (insn(12) = '1') then -- return
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pc2 <= rst0(13 downto 1); -- LINE 167: ????
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else
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pc2 <= pc_plus_1(12 downto 0); -- LINE 169: truncation ????
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end if;
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end if;
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end process;
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-- LINE 172:
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proc_next:
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process(sys_clk_i)
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begin
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if rising_edge(sys_clk_i) then
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if sys_rst_i = '1' then
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pc <= (others => '0');
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dsp <= (others => '0');
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st0 <= (others => '0');
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rsp <= (others => '0');
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else
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dsp <= dsp2;
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pc <= pc2;
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st0 <= st02;
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rsp <= rsp2;
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end if;
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end if;
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end process;
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end behave;
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