jens
529658b710
git-svn-id: http://moon:8086/svn/vhdl/trunk@128 cc03376c-175c-47c8-b038-4cd826a8556b
333 lines
7.9 KiB
VHDL
333 lines
7.9 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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use work.mips_instr.all;
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ENTITY tb_mips_muldiv IS
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END tb_mips_muldiv;
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ARCHITECTURE behavior OF tb_mips_muldiv IS
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COMPONENT muldiv is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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hilo_we : in std_logic;
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din_hi : in word_t;
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din_lo : in word_t;
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mul_divn : in std_logic;
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s_un : in std_logic;
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start : in std_logic;
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hilo_sel : in std_logic;
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busy : out std_logic;
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dout : out word_t
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10 ns;
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signal ENABLE_FAIL_REPORT : boolean := true;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal busy : std_logic;
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signal mul_divn : std_logic := '0';
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signal s_un : std_logic := '1';
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signal hilo_we : std_logic := '0';
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signal start : std_logic := '0';
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signal din_hi : word_t := (others => '-');
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signal din_lo : word_t := (others => '-');
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signal dout : word_t;
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signal hilo_sel : std_logic := '0';
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signal md_result : unsigned (2*word_t'length-1 downto 0) := (others => '0');
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signal ref_result : unsigned (2*word_t'length-1 downto 0);
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signal ref_hi : unsigned (word_t'length-1 downto 0);
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signal rtmp : unsigned (2*word_t'length-1 downto 0);
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signal tmp2 : unsigned (word_t'length-1 downto 0);
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signal check : std_logic;
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type word_array_t is array (natural range <>) of word_t;
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constant operands : word_array_t(0 to 63) :=
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(
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X"00000000",
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X"00000001",
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X"00000010",
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X"00000100",
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X"00001000",
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X"00010000",
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X"00100000",
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X"01000000",
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X"10000000",
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X"0000000F",
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X"000000FF",
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X"00000FFF",
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X"0000FFFF",
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X"000FFFFF",
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X"00FFFFFF",
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X"0FFFFFFF",
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X"12345678",
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X"23456789",
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X"7FFFFFFF",
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X"80000000",
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X"A541B3B9",
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X"80000001",
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X"80000010",
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X"80000100",
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X"80001000",
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X"80010000",
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X"80100000",
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X"81000000",
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X"87654321",
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X"98765432",
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X"FFFFFFFF",
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X"FFFFFFFE",
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X"FFFFFFFD",
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X"FFFFFFFB",
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X"FFFFFFF7",
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X"FFFFFFEF",
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X"FFFFFFDF",
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X"FFFFFFBF",
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X"FFFFFF7F",
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X"FFFFFEFF",
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X"FFFFFDFF",
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X"FFFFFBFF",
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X"FFFFF7FF",
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X"FFFFEFFF",
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X"FFFFDFFF",
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X"FFFFBFFF",
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X"FFFF7FFF",
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X"FFFEFFFF",
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X"FFFDFFFF",
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X"FFFBFFFF",
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X"FFF7FFFF",
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X"FFEFFFFF",
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X"FFDFFFFF",
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X"FFBFFFFF",
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X"FF7FFFFF",
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X"FEFFFFFF",
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X"FDFFFFFF",
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X"FBFFFFFF",
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X"F7FFFFFF",
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X"EFFFFFFF",
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X"DFFFFFFF",
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X"BFFFFFFF",
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X"CFFFFFFF",
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X"7FFFFFFF"
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);
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BEGIN
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uut: muldiv
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PORT MAP(
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rst => rst,
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clk => clk,
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hilo_we => hilo_we,
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din_hi => din_hi,
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din_lo => din_lo,
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mul_divn => mul_divn,
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s_un => s_un,
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start => start,
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hilo_sel => hilo_sel,
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busy => busy,
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dout => dout
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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REF_GEN: process
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begin
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if mul_divn = '0' then
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wait until rising_edge(clk) and check = '1';
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if s_un = '1' then
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rtmp <= unsigned(signed(md_result(31 downto 0)) * signed(din_lo));
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wait until rising_edge(clk);
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tmp2 <= unsigned(signed(rtmp(31 downto 0)) + signed(md_result(63 downto 32)));
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wait until rising_edge(clk);
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ref_hi <= tmp2(31 downto 0);
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else
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rtmp <= md_result(31 downto 0) * din_lo;
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wait until rising_edge(clk);
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tmp2 <= rtmp(31 downto 0) + md_result(63 downto 32);
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wait until rising_edge(clk);
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ref_hi <= tmp2(31 downto 0);
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end if;
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wait until rising_edge(clk);
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if din_lo /= X"00000000" then
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if ENABLE_FAIL_REPORT then
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assert din_hi = ref_hi report "Error on divison" severity failure;
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end if;
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end if;
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else
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wait until rising_edge(clk) and check = '1';
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if s_un = '1' then
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ref_result <= unsigned(signed(din_hi) * signed(din_lo));
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else
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ref_result <= unsigned(din_hi) * unsigned(din_lo);
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end if;
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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wait until rising_edge(clk);
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if ENABLE_FAIL_REPORT then
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assert ref_result = md_result report "Error on multiplication" severity failure;
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end if;
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end if;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait for 2*CLK_PERIOD;
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mul_divn <= '0';
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s_un <= '0';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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hilo_sel <= '0';
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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s_un <= '1';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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hilo_sel <= '0';
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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mul_divn <= '1';
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s_un <= '0';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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hilo_sel <= '0';
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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s_un <= '1';
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for i in 0 to operands'length-1 loop
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for j in 0 to operands'length-1 loop
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check <= '0';
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wait until rising_edge(clk) and busy = '0';
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din_hi <= operands(i);
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din_lo <= operands(j);
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start <= '1';
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wait until rising_edge(clk);
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start <= '0';
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hilo_sel <= '0';
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-- Read result
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wait until rising_edge(clk) and busy = '0';
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wait until rising_edge(clk);
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md_result(31 downto 0) <= dout;
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wait until rising_edge(clk);
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hilo_sel <= '1';
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wait until rising_edge(clk);
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md_result(63 downto 32) <= dout;
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check <= '1';
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wait until rising_edge(clk);
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check <= '0';
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wait for 8*CLK_PERIOD;
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end loop;
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end loop;
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wait;
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end process;
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END;
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