TLB queries come from pipeline if generic PIPE_ITLB or PIPE_DTLB is true. Cache query is then disabled.
If generic PIPE_ITLB or PIPE_DTLB set to false queries come from cache.
Piped TLB queries are piped translations with latency of two clocks. Piped translation allow physically indexed and physically tagged caches
- reworked PC logic
- prepared for individual BCUs in EX, MEM and WB stage
- changed LTS and LTU generation in ALU
Committed on the Free edition of March Hare Software CVSNT Server.
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git-svn-id: http://moon:8086/svn/vhdl/branches/BRANCH_MIPS_TLB@1016 cc03376c-175c-47c8-b038-4cd826a8556b
jens
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