jens
9edf6a70af
git-svn-id: http://moon:8086/svn/vhdl/trunk@1428 cc03376c-175c-47c8-b038-4cd826a8556b
110 lines
2.3 KiB
VHDL
110 lines
2.3 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 10:29:16 02/12/2010
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-- Design Name:
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-- Module Name: eval_asyn_fifo - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity eval_asyn_fifo is
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Port (
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din : in unsigned (31 downto 0);
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dout : out unsigned (31 downto 0);
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rst : in STD_LOGIC;
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clk_w : in STD_LOGIC;
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clk_r : in STD_LOGIC;
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full : out STD_LOGIC;
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empty : out STD_LOGIC;
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read : in STD_LOGIC;
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write : in STD_LOGIC);
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end eval_asyn_fifo;
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architecture Behavioral of eval_asyn_fifo is
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signal read0 : std_logic;
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signal empty0 : std_logic;
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signal write1 : std_logic;
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signal full1 : std_logic;
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signal dout0 : unsigned (31 downto 0);
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begin
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read0 <= not full1;
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write1 <= not empty0;
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uut0: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => 4,
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data_width => 32,
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almost_full_thresh => 6,
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almost_empty_thresh => 2,
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allow_full_writes => false,
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allow_empty_reads => false,
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do_last_read_update => true
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)
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PORT MAP
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(
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rst => rst,
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clk_w => clk_w,
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clk_r => clk_r,
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we => write,
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re => read0,
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data_w => din,
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data_r => dout0,
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fifo_full => full,
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fifo_empty => empty0,
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fifo_afull => open,
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fifo_aempty => open
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);
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uut1: entity work.fifo_sync
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GENERIC MAP
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(
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addr_width => 10,
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data_width => 32,
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almost_full_thresh => 6,
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almost_empty_thresh => 2,
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allow_full_writes => false,
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allow_empty_reads => false,
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do_last_read_update => true
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)
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PORT MAP
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(
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rst => rst,
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clk => clk_r,
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we => write1,
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re => read,
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data_w => dout0,
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data_r => dout,
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fifo_full => full1,
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fifo_empty => empty,
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fifo_afull => open,
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fifo_aempty => open
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);
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end Behavioral;
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