Files
vhdl/lib/CPUs/MIPS/sim/asm/faculty.s
T
jens cd2640e9c6 Initial revision
Committed on the Free edition of March Hare Software CVSNT Server.
Upgrade to CVS Suite for more features and support:
http://march-hare.com/cvsnt/


git-svn-id: http://moon:8086/svn/vhdl/trunk@986 cc03376c-175c-47c8-b038-4cd826a8556b
2013-07-24 18:13:16 +00:00

256 lines
3.6 KiB
ArmAsm

.file 1 "faculty.c"
.set nobopt
.text
.align 2
.globl faculty
.ent faculty
faculty:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
li $7,1 # 0x1
slt $2,$7,$6
.set noreorder
.set nomacro
beq $2,$0,$L7
sw $4,0($5)
.set macro
.set reorder
addiu $5,$5,4
$L5:
lw $2,-4($5)
mult $2,$7
addiu $7,$7,1
slt $3,$7,$6
mflo $2
sw $2,0($5)
.set noreorder
.set nomacro
bne $3,$0,$L5
addiu $5,$5,4
.set macro
.set reorder
$L7:
.set noreorder
.set nomacro
j $31
move $2,$7
.set macro
.set reorder
.end faculty
.align 2
.globl saus
.ent saus
saus:
.frame $sp,0,$31 # vars= 0, regs= 0/0, args= 0, gp= 0
.mask 0x00000000,0
.fmask 0x00000000,0
li $2,-2147483648 # 0xffffffff80000000
sll $4,$4,24
sra $4,$4,24
ori $5,$2,0x4
ori $3,$2,0x8
$L10:
lbu $2,0($3)
andi $2,$2,0x2
bne $2,$0,$L10
sb $4,0($5)
j $31
.end saus
.align 2
.globl sputs
.ent sputs
sputs:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-8
.fmask 0x00000000,0
addiu $sp,$sp,-32
sw $17,20($sp)
sw $16,16($sp)
sw $31,24($sp)
move $16,$4
lb $4,0($4)
.set noreorder
.set nomacro
j $L18
move $17,$16
.set macro
.set reorder
$L19:
.set noreorder
.set nomacro
jal saus
addiu $16,$16,1
.set macro
.set reorder
lb $4,0($16)
$L18:
.set noreorder
.set nomacro
bne $4,$0,$L19
subu $2,$16,$17
.set macro
.set reorder
lw $31,24($sp)
lw $17,20($sp)
lw $16,16($sp)
.set noreorder
.set nomacro
j $31
addiu $sp,$sp,32
.set macro
.set reorder
.end sputs
.align 2
.globl print_word
.ent print_word
print_word:
.frame $sp,32,$31 # vars= 0, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-8
.fmask 0x00000000,0
addiu $sp,$sp,-32
sw $17,20($sp)
sw $16,16($sp)
sw $31,24($sp)
move $16,$4
li $17,7 # 0x7
srl $3,$16,28
$L29:
sltu $2,$3,10
addiu $17,$17,-1
sll $16,$16,4
.set noreorder
.set nomacro
bne $2,$0,$L25
addiu $4,$3,48
.set macro
.set reorder
addiu $4,$3,55
$L25:
jal saus
.set noreorder
.set nomacro
bgez $17,$L29
srl $3,$16,28
.set macro
.set reorder
lw $31,24($sp)
lw $17,20($sp)
lw $16,16($sp)
.set noreorder
.set nomacro
j $31
addiu $sp,$sp,32
.set macro
.set reorder
.end print_word
.section .rodata.str1.4,"aMS",@progbits,1
.align 2
$LC0:
.ascii "MIPS R3000 CPU\r\n"
.ascii "Ready\r\n\000"
.text
.align 2
.globl main
.ent main
main:
.frame $sp,136,$31 # vars= 104, regs= 3/0, args= 16, gp= 0
.mask 0x80030000,-8
.fmask 0x00000000,0
lw $2,$LC0
lw $3,$LC0+4
addiu $sp,$sp,-136
sw $2,96($sp)
sw $3,100($sp)
lw $2,$LC0+8
lw $3,$LC0+12
sw $2,104($sp)
sw $3,108($sp)
lw $2,$LC0+16
lw $3,$LC0+20
li $7,-2147483648 # 0xffffffff80000000
ori $8,$7,0x9
sw $2,112($sp)
sw $3,116($sp)
ori $7,$7,0x8
li $3,85
sw $16,120($sp)
li $2,53
addiu $16,$sp,16
sb $2,0($8)
move $4,$16
sb $3,0($7)
move $5,$0
li $6,80 # 0x50
sw $31,128($sp)
.set noreorder
.set nomacro
jal memset
sw $17,124($sp)
.set macro
.set reorder
.set noreorder
.set nomacro
jal sputs
addiu $4,$sp,96
.set macro
.set reorder
li $3,1 # 0x1
sw $3,92($sp)
li $4,1 # 0x1
move $5,$16
li $6,20 # 0x14
.set noreorder
.set nomacro
jal faculty
move $17,$16
.set macro
.set reorder
li $16,19 # 0x13
$L36:
lw $4,0($17)
.set noreorder
.set nomacro
jal print_word
addiu $16,$16,-1
.set macro
.set reorder
.set noreorder
.set nomacro
jal saus
li $4,13 # 0xd
.set macro
.set reorder
.set noreorder
.set nomacro
jal saus
li $4,10 # 0xa
.set macro
.set reorder
.set noreorder
.set nomacro
bgez $16,$L36
addiu $17,$17,4
.set macro
.set reorder
$L37:
j $L37
.end main