jens
407a33db94
git-svn-id: http://moon:8086/svn/vhdl/trunk@1277 cc03376c-175c-47c8-b038-4cd826a8556b
253 lines
6.7 KiB
VHDL
253 lines
6.7 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: testbench for system test using Xilinx ML-402
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use work.spi_types.all;
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ENTITY tb_spi IS
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END tb_spi;
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ARCHITECTURE behavior OF tb_spi IS
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constant CLK_PERIOD : time := 10 ns;
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signal CLK : std_logic := '1';
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signal RST : std_logic := '1';
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signal mst_cmd_vld : STD_LOGIC := '0';
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signal mst_cmd_rdy : STD_LOGIC;
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signal mst_cmd : cmd_t;
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signal mst_din_vld : STD_LOGIC := '0';
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signal mst_din_rdy : STD_LOGIC;
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signal mst_din : unsigned(31 downto 0) := (others => '0');
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signal mst_dout : unsigned(31 downto 0);
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signal mst_dout_vld : STD_LOGIC;
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signal mst_dout_re : STD_LOGIC := '1';
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signal mst_shift_en : STD_LOGIC := '1';
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signal mosi : STD_LOGIC;
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signal miso : STD_LOGIC := '0';
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signal mst_clk : STD_LOGIC;
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signal ctrl : ctrl_t;
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signal status : status_t;
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signal mso : STD_LOGIC;
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signal mst_rx_data : unsigned(31 downto 0);
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signal slv_rx_shiftreg : unsigned(31 downto 0) := (others => '0');
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signal slv_tx_shiftreg : unsigned(31 downto 0) := (others => '0');
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signal slv_rx_valid_pipe : unsigned(31 downto 0) := (others => '0');
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signal slv_rx_data : unsigned(31 downto 0) := (others => '0');
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BEGIN
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ctrl.cpol <= '0';
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ctrl.cpha <= '0';
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ctrl.msb_first <= '1';
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inst_spi_tx : entity work.spi_tx
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GENERIC MAP
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(
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word_width => 32
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)
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PORT MAP
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(
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rst => RST,
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clk => CLK,
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cmd_vld => mst_cmd_vld,
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cmd_rdy => mst_cmd_rdy,
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cmd => mst_cmd,
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din_vld => mst_din_vld,
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din_rdy => mst_din_rdy,
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din => mst_din,
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dout_re => mst_dout_re,
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dout_vld => mst_dout_vld,
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dout => mst_dout,
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shift_en => mst_shift_en,
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mosi => mosi,
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miso => miso,
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sclk => mst_clk,
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mso => mso,
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ctrl => ctrl,
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status => status
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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CLK <= not CLK;
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end process;
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RX_SLAVE_SIM_SHIFT_REG: process(mst_clk)
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begin
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if rising_edge(mst_clk) then
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if mso = '1' then
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if slv_rx_valid_pipe(slv_rx_valid_pipe'left) = '1' then
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slv_rx_valid_pipe <= (slv_rx_valid_pipe'left downto 1 => '0') & '1';
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else
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slv_rx_valid_pipe <= slv_rx_valid_pipe(slv_rx_valid_pipe'left-1 downto 0) & '1';
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end if;
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slv_rx_shiftreg <= slv_rx_shiftreg(slv_rx_shiftreg'left-1 downto 0) & mosi;
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slv_tx_shiftreg <= slv_tx_shiftreg(slv_tx_shiftreg'left-1 downto 0) & mosi;
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else
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slv_tx_shiftreg <= slv_tx_shiftreg(slv_tx_shiftreg'left-1 downto 0) & mosi;
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end if;
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end if;
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end process;
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miso <= slv_tx_shiftreg(slv_tx_shiftreg'left);
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RX_SLAVE_SIM_DATA_REG: process(clk)
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variable data_vld : unsigned(1 downto 0);
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begin
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if mso = '0' then
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data_vld := "00";
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elsif rising_edge(clk) then
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data_vld(1) := data_vld(0);
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data_vld(0) := slv_rx_valid_pipe(slv_rx_valid_pipe'left);
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if data_vld(0) = '1' and data_vld(1) = '0' then
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slv_rx_data <= slv_rx_shiftreg;
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end if;
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end if;
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end process;
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MASTER_TX_DATA_REG: process(clk)
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begin
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if rising_edge(clk) then
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if mst_dout_vld = '1' then
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mst_rx_data <= mst_dout;
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end if;
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end if;
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end process;
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-- Master
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STIMULUS: process
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begin
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wait for 600*CLK_PERIOD;
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RST <= '0';
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wait for 6*CLK_PERIOD;
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wait for 600*CLK_PERIOD;
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wait until rising_edge(CLK);
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mst_din <= X"C355AAC1";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(32, 32);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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--------------------------------------------------------
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wait until rising_edge(CLK);
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mst_din <= X"C3AA55C1";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(64, 64);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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wait for 200*CLK_PERIOD;
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din <= X"83AAFF05";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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--------------------------------------------------------
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wait until rising_edge(CLK);
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mst_din <= X"C355AAC1";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(64, 32);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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--------------------------------------------------------
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mst_din <= X"00000000";
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for i in 0 to 16 loop
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wait until rising_edge(CLK);
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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mst_din <= mst_din + 1;
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(64, 32);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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wait until rising_edge(CLK) and mso = '1';
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wait until rising_edge(CLK) and mso = '0';
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end loop;
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--------------------------------------------------------
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wait until rising_edge(CLK);
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mst_din <= X"C355AA00";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(32, 24);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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--------------------------------------------------------
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wait until rising_edge(CLK);
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mst_din <= X"C355AAC1";
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mst_din_vld <= '1';
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wait until rising_edge(CLK) and mst_din_rdy = '1';
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mst_din_vld <= '0';
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wait until rising_edge(CLK);
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mst_cmd <= to_cmd(24, 32);
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mst_cmd_vld <= '1';
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wait until rising_edge(CLK) and mst_cmd_rdy = '1';
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mst_cmd_vld <= '0';
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wait;
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end process;
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END;
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