270 lines
6.7 KiB
VHDL
270 lines
6.7 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: SDRAM controller
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-- This file: SDRAM command controller
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.sdram_config.all;
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use work.sdram_types.all;
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entity sdram_cmd is
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Generic (BL : natural := 2);
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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enable : in STD_LOGIC;
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u_tag_in : in user_tag_t;
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u_tag_out : out user_tag_t;
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phy_ctrl : out phy_ctrl_t;
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cmd : in sdr_cmd_t;
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cmd_we : in STD_LOGIC;
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cmd_ack : out STD_LOGIC;
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col_addr : in col_addr_t;
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mode_word : in mode_word_t;
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sdr_cmd_ctrl : out sdr_cmd_lines_t;
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sdr_addr : out sdr_addr_t;
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sdr_ba : out sdr_ba_t
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);
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end sdram_cmd;
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architecture behaviour of sdram_cmd is
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signal st_sdr, st_sdr_next : sdr_state_t;
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signal cc_preset : natural range 0 to 10;
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signal cc_load_en : std_logic;
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signal cycle_finished : std_logic;
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signal burst_preset : natural range 0 to 3;
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signal burst_load_en : std_logic;
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signal burst_finished : std_logic;
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begin
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u_tag_out <= u_tag_in;
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------------------------------------------------------------------------------------------
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fsm_sdr_state:
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process (st_sdr, cmd, cmd_we, cycle_finished, burst_finished, mode_word, enable, col_addr)
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begin
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st_sdr_next <= st_sdr;
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sdr_cmd_ctrl <= COMMAND(SD_NOP);
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cc_load_en <= '0';
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cc_preset <= TIMING(cmd);
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burst_load_en <= '0';
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cmd_ack <= '0';
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burst_preset <= BL/2-1;
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phy_ctrl.re <= '0';
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phy_ctrl.drive_en <= '0';
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phy_ctrl.we <= '0';
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phy_ctrl.utag_we <= '0';
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sdr_addr <= mode_word(sdr_addr_t'left downto sdr_addr_t'right);
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sdr_ba <= mode_word(mode_word_t'left downto mode_word_t'left-1);
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case st_sdr is
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when PWR_DOWN =>
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sdr_cmd_ctrl <= COMMAND(SD_DESELECT);
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if enable = '1' then
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st_sdr_next <= IDLE;
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end if;
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when PRECHARGE =>
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if cycle_finished = '1' then
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st_sdr_next <= IDLE;
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end if;
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when MODE =>
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if cycle_finished = '1' then
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st_sdr_next <= IDLE;
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end if;
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when IDLE =>
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if cmd_we = '1' then
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cmd_ack <= '1';
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cc_load_en <= '1';
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cc_preset <= TIMING(cmd);
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sdr_cmd_ctrl <= COMMAND(cmd);
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case cmd is
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when SD_PRE =>
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st_sdr_next <= PRECHARGE;
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sdr_addr(BIT_PRE_ALL) <= mode_word(BIT_PRE_ALL);
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when SD_LMR =>
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st_sdr_next <= MODE;
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when SD_ACT =>
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st_sdr_next <= ROW_ACT;
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when SD_AR =>
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st_sdr_next <= AUTO_REF;
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when others => null;
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end case;
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end if;
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when ROW_ACT =>
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if cycle_finished = '1' then
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if cmd_we = '1' then
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cmd_ack <= '1';
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burst_load_en <= '1';
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cc_load_en <= '1';
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cc_preset <= TIMING(cmd);
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sdr_cmd_ctrl <= COMMAND(cmd);
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case cmd is
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when SD_PRE =>
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st_sdr_next <= PRECHARGE;
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when SD_READ =>
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phy_ctrl.utag_we <= '1';
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st_sdr_next <= READ;
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sdr_addr(col_addr_t'range) <= col_addr;
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when SD_WRITE =>
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phy_ctrl.utag_we <= '1';
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phy_ctrl.drive_en <= '1';
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st_sdr_next <= WRITE;
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sdr_addr(col_addr_t'range) <= col_addr;
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when others => null;
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end case;
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end if;
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end if;
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when WRITE =>
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phy_ctrl.drive_en <= '1';
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phy_ctrl.we <= '1';
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if burst_finished = '1' then
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if cmd_we = '1' and cmd = SD_WRITE then
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sdr_addr(col_addr_t'range) <= col_addr;
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cmd_ack <= '1';
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burst_load_en <= '1';
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sdr_cmd_ctrl <= COMMAND(cmd);
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phy_ctrl.utag_we <= '1';
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else
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phy_ctrl.drive_en <= '0';
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cc_load_en <= '1';
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cc_preset <= TIMING(SD_WRITE)+1;
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st_sdr_next <= ROW_ACT;
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end if;
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end if;
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when READ =>
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phy_ctrl.re <= '1';
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if burst_finished = '1' then
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if cmd_we = '1' and cmd = SD_READ then
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sdr_addr(col_addr_t'range) <= col_addr;
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cmd_ack <= '1';
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burst_load_en <= '1';
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sdr_cmd_ctrl <= COMMAND(cmd);
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phy_ctrl.utag_we <= '1';
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else
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cc_load_en <= '1';
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cc_preset <= TIMING(SD_READ);
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st_sdr_next <= ROW_ACT;
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end if;
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end if;
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when WRITE_A => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when READ_A => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when BURST_STOP => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when SELF_REF => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when PRE_PWR_DOWN => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when ACT_PWR_DOWN => -- not implemented yet
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cmd_ack <= '1';
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st_sdr_next <= IDLE;
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when AUTO_REF =>
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if cycle_finished = '1' then
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st_sdr_next <= IDLE;
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end if;
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when others =>
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st_sdr_next <= IDLE;
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end case;
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end process;
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fsm_sdr_state_next:
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process (rst, clk)
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begin
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if rst = '1' then
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st_sdr <= PWR_DOWN;
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elsif rising_edge(clk) then
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st_sdr <= st_sdr_next;
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end if;
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end process;
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------------------------------------------------------------------------------------------
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cycle_counter:
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process (rst, clk)
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variable cycle_cnt : natural range 0 to 10;
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begin
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if rst = '1' then
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cycle_cnt := 0;
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cycle_finished <= '0';
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elsif rising_edge(clk) then
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cycle_finished <= '0';
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if cc_load_en = '1' then
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cycle_cnt := cc_preset;
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elsif cycle_cnt /= 0 then
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cycle_cnt := cycle_cnt - 1;
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else
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cycle_finished <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------------------
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burst_counter:
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process (rst, clk)
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variable burst_cnt : natural range 0 to 3;
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begin
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if rst = '1' then
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burst_cnt := 0;
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elsif rising_edge(clk) then
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burst_finished <= '0';
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if burst_load_en = '1' then
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burst_cnt := burst_preset;
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elsif burst_cnt /= 0 then
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burst_cnt := burst_cnt - 1;
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end if;
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if burst_cnt = 0 then
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burst_finished <= '1';
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end if;
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end if;
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end process;
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------------------------------------------------------------------------------------------
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end behaviour;
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