jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
277 lines
6.6 KiB
VHDL
277 lines
6.6 KiB
VHDL
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 15:41:12 06/05/2007
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-- Design Name:
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-- Module Name: ac_out - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity ac_out is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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sync_tx : out std_logic;
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cmd_addr : in unsigned (19 downto 0);
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cmd_data : in unsigned (19 downto 0);
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cmd_we : in std_logic;
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pcm_in_addr : in unsigned (3 downto 0);
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pcm_in_data : in unsigned (19 downto 0);
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pcm_in_we : in std_logic;
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ac_reset : in std_logic;
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ac_bit_clk : in std_logic;
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ac_sdata_out : out std_logic;
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ac_ssync : out std_logic
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);
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end ac_out;
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architecture Behavioral of ac_out is
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------------------------------------------------------------------
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COMPONENT singleshot
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GENERIC (mode : integer);
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PORT(
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rst : IN std_logic;
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clk : IN std_logic;
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input : IN std_logic;
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output : OUT std_logic
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);
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END COMPONENT;
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------------------------------------------------------------------
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subtype tag_t is UNSIGNED(15 downto 0);
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subtype slot_valid_t is UNSIGNED(1 to 12);
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signal slot_valid : slot_valid_t;
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subtype slot_t is UNSIGNED(19 downto 0);
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type slot_array_t is array (natural range <>) of slot_t;
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signal data_array : slot_array_t (1 to 12);
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signal tx_reg : UNSIGNED(19 downto 0);
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signal last_slot, ssync : STD_LOGIC;
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type sac_t is (ac_idle, ac_tag, ac_data);
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signal sac, snac : sac_t;
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subtype bitcnt_t is integer range 0 to 19;
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subtype slotcnt_t is integer range 0 to 12;
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signal bitcnt : bitcnt_t;
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signal bitcnt_rst, bitcnt_en : STD_LOGIC;
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signal slotcnt : slotcnt_t;
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signal slotcnt_rst, slotcnt_en : STD_LOGIC;
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signal slot_start : STD_LOGIC;
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------------------------------------------------------------------
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function CreateTag(slot_valid : slot_valid_t) return tag_t is
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variable tag : tag_t := (others => '0');
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begin
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tag := (others => '0');
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for i in slot_valid_t'range loop
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tag(15-i) := slot_valid(i);
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if slot_valid(i) = '1' then
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tag(15) := '1';
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end if;
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end loop;
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tag(0) := '0'; -- ID0
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tag(1) := '0'; -- ID1
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tag(2) := '0'; -- Reserved
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-- tag(15) := '1'; -- Frame is valid
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return tag;
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end CreateTag;
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begin
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------------------------------------------------------------------
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proc_slot_reg:
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process (clk, cmd_addr, cmd_data, cmd_we, pcm_in_data, pcm_in_we, pcm_in_addr, last_slot)
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variable slot_id : integer range 0 to 12;
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begin
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slot_id := to_integer(pcm_in_addr);
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if rising_edge(clk) then
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if rst = '1' then
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for i in data_array'range(1) loop
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data_array(i) <= (others => '0');
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end loop;
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slot_valid <= (others => '0');
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elsif last_slot = '1' then
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slot_valid <= (others => '0');
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else
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if cmd_we = '1' then
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slot_valid(1) <= '1';
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slot_valid(2) <= '1';
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data_array(1) <= cmd_addr;
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data_array(2) <= cmd_data;
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end if;
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if pcm_in_we = '1' then
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if (slot_id > 2) then
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data_array(slot_id) <= pcm_in_data;
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slot_valid(slot_id) <= '1';
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end if;
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end if;
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end if;
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end if;
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end process;
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-------------------------------------------------------------
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-- proc_slot_count
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-------------------------------------------------------------
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proc_slot_count:
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process (slotcnt_rst, ac_bit_clk, slotcnt_en, slotcnt)
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begin
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if rising_edge(ac_bit_clk) then
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if slotcnt_rst = '1' then
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slotcnt <= slotcnt_t'low;
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elsif slotcnt_en = '1' then
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if slotcnt /= slotcnt_t'high then
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slotcnt <= slotcnt + 1;
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else
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slotcnt <= slotcnt_t'low;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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-- proc_bit_count
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------------------------------------------------------------------
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proc_bit_count:
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process (bitcnt_rst, ac_bit_clk, bitcnt_en, bitcnt)
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begin
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if rising_edge(ac_bit_clk) then
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if bitcnt_rst = '1' then
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bitcnt <= bitcnt_t'low;
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elsif bitcnt_en = '1' then
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if bitcnt /= bitcnt_t'high then
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bitcnt <= bitcnt + 1;
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else
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bitcnt <= bitcnt_t'low;
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end if;
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_ac_fsm:
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process (bitcnt, slotcnt, sac)
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begin
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snac <= sac;
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bitcnt_rst <= '0';
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bitcnt_en <= '1';
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slotcnt_rst <= '0';
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slotcnt_en <= '0';
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slot_start <= '0';
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ssync <= '0';
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if bitcnt = 0 then
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slot_start <= '1';
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end if;
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case sac is
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when ac_idle =>
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bitcnt_rst <= '1';
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slotcnt_rst <= '1';
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snac <= ac_tag;
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when ac_tag =>
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ssync <= '1';
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if (bitcnt = 15) then
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slotcnt_en <= '1';
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bitcnt_rst <= '1';
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snac <= ac_data;
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end if;
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when ac_data =>
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if bitcnt = 19 then
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slotcnt_en <= '1';
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if slotcnt = 12 then
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slotcnt_rst <= '1';
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snac <= ac_tag;
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end if;
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end if;
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when others => null;
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end case;
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end process;
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proc_ac_fsm_next:
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process (ac_reset, ac_bit_clk, snac)
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begin
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if ac_reset = '1' then
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sac <= ac_idle;
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elsif rising_edge(ac_bit_clk) then
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sac <= snac;
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end if;
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end process;
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------------------------------------------------------------------
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proc_tx_shift_reg:
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process (ac_reset, ac_bit_clk, tx_reg, ssync, slot_valid, data_array)
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begin
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if ac_reset = '1' then
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tx_reg <= (others => '0');
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elsif rising_edge(ac_bit_clk) then
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last_slot <= '0';
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if slot_start = '1' then
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if ssync = '1' then
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tx_reg <= CreateTag(slot_valid) & "0000";
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else
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if slotcnt /= 0 then
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tx_reg <= data_array(slotcnt);
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if slotcnt = 12 then
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last_slot <= '1';
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end if;
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end if;
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end if;
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else
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tx_reg <= tx_reg(tx_reg'left-1 downto 0) & '0';
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end if;
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end if;
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end process;
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------------------------------------------------------------------
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proc_ac_sync_out:
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process (ac_reset, ac_bit_clk, ssync, tx_reg)
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begin
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if ac_reset = '1' then
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ac_ssync <= '0';
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ac_sdata_out <= '0';
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elsif rising_edge(ac_bit_clk) then
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ac_ssync <= ssync;
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ac_sdata_out <= tx_reg(tx_reg'left);
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end if;
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end process;
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------------------------------------------------------------------
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singleshot_inst1: singleshot
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GENERIC MAP (
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mode => 0)
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PORT MAP(
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rst => rst,
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clk => clk,
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input => last_slot,
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output => sync_tx
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);
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end Behavioral;
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