jens 3709ffcefe - async_port_timing: Changed names and timing diagram ...

to reflect V1.6 of async_port_wb.vhdl

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git-svn-id: http://moon:8086/svn/vhdl/trunk@536 cc03376c-175c-47c8-b038-4cd826a8556b

2009-10-27 21:42:08 +00:00

..

ac97_ctrl

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

CPUs

- async_port_timing: Changed names and timing diagram

2009-10-27 21:42:08 +00:00

FIFO

- renamed

2009-01-30 21:22:25 +00:00

filter

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

fix_std

Initial import

2008-08-23 08:20:30 +00:00

fixed

deleted

2009-01-11 15:31:42 +00:00

fixed_ja

Initial import

2008-08-23 08:20:30 +00:00

jasm

Initial import

2008-08-23 08:20:30 +00:00

misc

- redesigned FSM. Zero leadin, zeroleadout and zero release is now possible

2009-10-27 21:25:36 +00:00

PCK_FIO-1.16

Initial import

2008-08-23 08:20:30 +00:00

PCK_FIO-2002.7

Initial import

2008-08-23 08:20:30 +00:00

radio

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SDRAM

- renamed fifo_*sync_ctrl

2009-01-30 21:30:21 +00:00

SSRAM

- Using MODELSIM_HOME environment variable

2008-10-23 21:21:24 +00:00

uart

- removed force-TX-IRQ and TX-IRQ acknowledge

2009-10-24 20:27:57 +00:00

VGA_ctrl

- added test color register base + 0x80

2009-05-01 19:26:43 +00:00