jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
77 lines
2.2 KiB
VHDL
77 lines
2.2 KiB
VHDL
--------------------------------------------------------------------------
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--
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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--
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--------------------------------------------------------------------------
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--
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-- $RCSfile: reg_file-behaviour.vhdl,v $ $Revision: 2.1 $ $Date: 1993/11/02 19:16:52 $
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--
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--------------------------------------------------------------------------
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--
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-- Behavioural architecture of register file.
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--
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architecture behaviour of reg_file is
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begin
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reg: process (a1, a2, a3, d3, write_en)
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use work.bv_arithmetic.bv_to_natural;
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constant all_zeros : dlx_word := X"0000_0000";
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type register_array is array (reg_index range 1 to 31) of dlx_word;
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variable register_file : register_array;
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variable reg_index1, reg_index2, reg_index3 : reg_index;
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begin
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-- do write first if enabled
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--
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if write_en = '1' then
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reg_index3 := bv_to_natural(a3);
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if reg_index3 /= 0 then
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register_file(reg_index3) := d3;
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end if;
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end if;
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--
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-- read port 1
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--
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reg_index1 := bv_to_natural(a1);
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if reg_index1 /= 0 then
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q1 <= register_file(reg_index1) after Tac;
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else
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q1 <= all_zeros after Tac;
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end if;
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--
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-- read port 2
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--
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reg_index2 := bv_to_natural(a2);
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if reg_index2 /= 0 then
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q2 <= register_file(reg_index2) after Tac;
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else
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q2 <= all_zeros after Tac;
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end if;
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end process reg;
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end behaviour;
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