138 lines
3.4 KiB
VHDL
138 lines
3.4 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: JIPS top file
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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library work;
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use work.mips_types.all;
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entity mips_embedded_syn is
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Port
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(
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sys_rst_n_in : in STD_LOGIC;
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sys_clk_in : in STD_LOGIC;
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sys_dip : in STD_LOGIC_VECTOR (7 downto 0);
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sys_btn : in STD_LOGIC_VECTOR (8 downto 0);
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sys_led : out STD_LOGIC_VECTOR (7 downto 0);
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sys_rx : in STD_LOGIC;
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sys_tx : out STD_LOGIC;
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sys_error : out STD_LOGIC_VECTOR (1 downto 0)
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);
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end mips_embedded_syn;
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architecture struct of mips_embedded_syn is
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COMPONENT mips_embedded
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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halt : in STD_LOGIC;
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int : in unsigned(5 downto 0);
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rxd : in STD_LOGIC;
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txd : out STD_LOGIC;
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dout : out word_t
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);
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END COMPONENT;
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signal dout : word_t;
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signal rst : STD_LOGIC;
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signal clk : STD_LOGIC;
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signal halt : STD_LOGIC;
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signal int : unsigned(5 downto 0);
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signal btn_r : unsigned (8 downto 0);
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signal dip_r : unsigned (7 downto 0);
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begin
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-------------------------------------------------------------------
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inst_mips_embedded: mips_embedded
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PORT MAP
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(
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rst => rst,
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clk => clk,
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halt => halt,
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int => int,
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rxd => sys_rx,
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txd => sys_tx,
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dout => dout
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);
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clk <= sys_clk_in;
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rst <= not sys_rst_n_in;
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ERR_LED_reg:
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process(rst, clk)
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begin
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if rst = '1' then
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sys_error <= (others => '1');
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elsif rising_edge(clk) then
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sys_error <= STD_LOGIC_VECTOR(dout(31 downto 30));
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end if;
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end process;
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LED_reg:
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process(rst, clk)
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begin
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if rst = '1' then
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sys_led <= (others => '0');
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elsif rising_edge(clk) then
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sys_led <= STD_LOGIC_VECTOR(dout(7 downto 0));
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end if;
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end process;
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DIP_reg:
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process(rst, clk)
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begin
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if rst = '1' then
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dip_r <= (others => '0');
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elsif rising_edge(clk) then
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dip_r <= unsigned(sys_dip);
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end if;
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end process;
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BTN_reg:
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process(rst, clk)
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begin
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if rst = '1' then
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btn_r <= (others => '0');
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elsif rising_edge(clk) then
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btn_r <= unsigned(sys_btn);
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end if;
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end process;
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halt <= btn_r(4) after 6.5 ns;
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int(0) <= dip_r(0) and btn_r(3) after 1 ns;
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int(1) <= dip_r(1) and btn_r(3) after 1 ns;
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int(2) <= dip_r(2) and btn_r(3) after 1 ns;
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int(3) <= dip_r(3) and btn_r(3) after 1 ns;
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int(4) <= dip_r(4) and btn_r(3) after 1 ns;
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int(5) <= dip_r(5) and btn_r(3) after 1 ns;
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-------------------------------------------------------------------
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end struct;
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