495 lines
15 KiB
Ruby
Executable File
495 lines
15 KiB
Ruby
Executable File
#!/usr/bin/env ruby
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# ----------------------------------------------------------------------
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# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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# This file: A small assembler for the JCPU
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# Copyright (C) 2007 J. Ahrensfeld
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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# For questions and ideas, please contact the author at jens@jayfield.org
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# ---------------------------------------------------------------------
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arg = $*
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MAX_SIZE_ROM = 1024
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PROJECT_NAME = arg.to_s.gsub(/\..*/, "")
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ENTITY_NAME = "rom"
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ENTITY_DATA_TYPE = "inst_t"
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ENTITY_ADDR_TYPE = "inst_addr_t"
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OPC_LIST_NAME = "/cygdrive/w/vhdl/lib/CPUs/JCpu/tools/opc.list"
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# --------------------------------------------------------
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# Open file
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# --------------------------------------------------------
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filename = arg.to_s
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if !File.exists?(filename)
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STDERR.puts "#{filename} does not exist"
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exit 1
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end
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# --------------------------------------------------------
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# Pass 1
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# --------------------------------------------------------
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lc = 0 # Line counter
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pc = 0 # Program counter
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chip_dc = [0,0,0,0] # chip data counter
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xmem_dc = 0 # xmem data counter
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curr_segment = "UNDEF";
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page = 0
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label_list=[[],[]]
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instr_list=[nil]
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file = File.open(filename, "r")
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file.each do |raw_line|
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lc += 1
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# Make all upper case
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iline = "#{raw_line}".strip.upcase
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# Remove comments
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iline = iline.gsub(/;.*/, "")
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# Split instruction at spaces
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iline_member = iline.split(" ")
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if iline_member[0] == nil
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next
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end
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mc = 0;
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label = nil
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clean_line = nil
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if (iline_member[0] =~ /\w+:/)
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mc += 1
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label = iline_member[0].delete(":")
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if label_list.rindex(label) != nil
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STDERR.puts format("Error in line %d: Duplicate label \"%s\" found", lc, label)
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exit 1
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end
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end
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case iline_member[mc]
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when nil
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value = format("0x%3.3X",pc)
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when "EQU"
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if 0 == (iline_member[mc+1] =~ /\d+/)
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value = format("0x%2.2X",eval(iline_member[mc+1..iline_member.nitems].to_s))
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else
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value = iline_member[mc+1]
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end
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when "ORG", "CODE"
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pc = eval(iline_member[mc+1..iline_member.nitems].to_s)
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value = format("0x%3.3X",pc)
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when "CDATA", "CMEM"
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if iline_member[mc+1] == nil
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STDERR.puts format("Error in line %d: CDATA needs argument!", lc)
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exit 1
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end
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curr_segment = "CMEM";
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page = iline_member[mc+1].to_i(16)
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when "XDATA", "XMEM"
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curr_segment = "XMEM";
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when "DC"
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len = 0;
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iline.split("DC")[1].delete("0x").scan(/[0-9A-Fa-f]+/).each do |byte|
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len += 1
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end
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if curr_segment == "CMEM"
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STDERR.puts format("Error in line %d: CDATA cannot be initialized!", lc)
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exit 1
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else
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value = format("0x%2.2X",xmem_dc)
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puts format("Found DC defining %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
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xmem_dc += len
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end
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when "DB"
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len = iline_member[mc+1].to_i
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if curr_segment == "CMEM"
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value = format("0x%2.2X",chip_dc[page])
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puts format("Found DB reserving %d bytes at 0x%4.4X in %s(%d)", len, chip_dc[page], curr_segment, page);
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chip_dc[page] += len
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else
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value = format("0x%2.2X",xmem_dc)
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puts format("Found DB reserving %d bytes at 0x%4.4X in %s", len, xmem_dc, curr_segment);
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xmem_dc += len
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end
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else
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op_line = iline_member[mc+1..iline_member.nitems].to_s
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value = format("0x%3.3X",pc)
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opc = iline_member[mc]
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if iline_member[mc+1] != nil
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op1 = op_line.gsub(/,+.*$/, "")
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end
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if iline_member[mc+2] != nil
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op2 = op_line.scan(/,.+$/).to_s.delete(", ")
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end
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if instr_list[pc] == nil
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instr_list[pc] = [lc, pc, opc , op1 , op2]
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pc += 1
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else
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STDERR.puts format("Error in line %d: Overlapping sections at %3.3X", lc, pc)
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exit 1
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end
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end;
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# Push labels
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if label
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label_list = label_list + [label, value]
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end
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end
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file.close
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# --------------------------------------------------------
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def instr(opcode)
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return format("\"%6.6B\" & X\"%3.3X\"",opcode ,0)
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end
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def tcl_bits(pc, opcode)
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return format("%10.10B%6.6B%12.12B",pc, opcode ,0)
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end
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def instr_k(opcode, k)
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return format("\"%6.6B\" & X\"%3.3X\"",opcode ,k)
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end
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def tcl_bits_k(pc, opcode, k)
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return format("%10.10B%6.6B%12.12B",pc, opcode ,k)
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end
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def instr_r(opcode, r)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode ,0, r)
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end
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def tcl_bits_r(pc, opcode, r)
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return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode ,0,r)
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end
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def instr_kr(opcode, k, r)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
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end
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def tcl_bits_kr(pc, opcode, k, r)
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return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
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end
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def instr_rk(opcode, r, k)
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return format("\"%6.6B\" & X\"%2.2X%X\"",opcode,k, r)
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end
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def tcl_bits_rk(pc, opcode, r, k)
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return format("%10.10B%6.6B%8.8B%4.4B",pc, opcode, k, r)
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end
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def instr_rr(opcode, ra, rb)
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return format("\"%6.6B\" & X\"%X%X%X\"",opcode,0, rb, ra)
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end
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def tcl_bits_rr(pc, opcode, ra, rb)
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return format("%10.10B%6.6B%4.4B%4.4B%4.4B",pc, opcode, 0, rb, ra)
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end
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# --------------------------------------------------------
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# Read mnemonic set
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# --------------------------------------------------------
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filename = OPC_LIST_NAME
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if !File.exists?(filename)
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STDERR.puts "#{filename} does not exist"
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exit 1
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end
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mnemo_list = []
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num_opcodes = 0
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file = File.open(filename, "r")
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file.each do |raw_line|
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mnemo_list[num_opcodes] = raw_line.split(" ")[1]
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num_opcodes += 1
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end
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# --------------------------------------------------------
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# Pass 2
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# --------------------------------------------------------
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pc = 0
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opc_start = 2
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num_errors = 0
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vhdl_trans_list = [nil]
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vhdl_comment_list = [nil]
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vhdl_tcl_list = [nil]
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instr_list.each do |instruct|
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# puts instruct
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if instruct == nil
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vhdl_trans_list[pc] = format("\"%6.6B\" & X\"%3.3X\"",0 ,0)
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vhdl_comment_list[pc] = format("0x%3.3X:", pc)
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vhdl_tcl_list[pc] = tcl_bits(pc, 0)
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pc += 1
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next
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end
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# determine arglen of instruction
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ilen = 0
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if instruct[opc_start+1] == nil
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arglen = 0
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elsif instruct[opc_start+2] == nil
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arglen = 1
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elsif instruct[opc_start+3] == nil
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arglen = 2
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end
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# Symbol substitution
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error = false
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for i in (1..3)
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subst_pos = opc_start+i
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if instruct[subst_pos] == nil
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next
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end
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expr_token = ""
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expr_subst = nil
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is_direct = true;
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# instruct[subst_pos] = instruct[subst_pos].delete(" ")
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# checks R0 .. R16, Mnemonics
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instr_str = instruct[subst_pos]
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if 0 == (instr_str =~ /\(.+\)/)
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instr_str = instr_str.delete("()")
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is_direct = false;
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end
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expr_token = instr_str.split(/\+|\-|\*|\//)[0]
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if (0 != (expr_token =~ /R[0-9]+/)) && (0 != (expr_token =~ /\d+/))
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idx = label_list.rindex(expr_token)
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if idx != nil
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expr_subst = label_list[idx+1]
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instruct[subst_pos] = instruct[subst_pos].gsub(expr_token, expr_subst)
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else
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STDERR.puts format("Error in line %d: Symbol \"%s\" not found", instruct[0], expr_token)
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error = true
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end
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end
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if expr_subst != nil
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if 0 == (expr_subst =~ /\d+/)
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if is_direct == true
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instruct[subst_pos] = format("0x%2.2X", eval(instruct[subst_pos]))
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else
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instruct[subst_pos] = format("(0x%2.2X)", eval(instruct[subst_pos]))
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end
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else
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if 0 != (expr_subst =~ /R[0-9]+/)
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STDERR.puts format("Error in line %d: Invalid expression \"%s\"", instruct[0], expr_subst)
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error = true
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end
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end
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end
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end
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# Parse operands
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reg = [0,0]
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kk = 0
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format = instruct[opc_start]
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for i in (0..1)
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if instruct[opc_start+i+1] =~ Regexp.new("R[0-9]+")
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# Check indirect addressing
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reg[i] = instruct[opc_start+i+1].delete("R()").to_i
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format += "|R"
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if reg[i] > 15
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STDERR.puts format("Error in line %d: Invalid register \"R%d\" specified", instruct[0], reg[i])
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error = true
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end
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else
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if instruct[opc_start+i+1] =~ Regexp.new("[0-9A-F]+")
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kk = instruct[opc_start+i+1].delete("()").to_i(16)
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format += "|K"
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end
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end
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if instruct[opc_start+i+1] =~ Regexp.new("\\(.+\\)")
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format += "i";
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end
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end
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# Output instruction
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opcode = mnemo_list.rindex(format).to_i
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mnemo = instruct[2];
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case format
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when "NOP", "HALT", "RET", "RETI"
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vhdl_trans_list[pc] = instr(opcode)
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vhdl_tcl_list[pc] = tcl_bits(pc, opcode)
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minstr_comment = format("0x%3.3X: %s", pc, mnemo)
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when "MOVC|R|Ri", "MOVX|R|Ri"
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vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
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vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
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minstr_comment = format("0x%3.3X: %s R%2.2d, (R%2.2d)", pc, mnemo, reg[0], reg[1])
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when "MOV|R|R", "SUB|R|R", "ADD|R|R", "AND|R|R", "OR|R|R", "XOR|R|R", "CMP|R|R"
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vhdl_trans_list[pc] = instr_rr(opcode, reg[0], reg[1]);
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vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[0], reg[1])
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minstr_comment = format("0x%3.3X: %s R%2.2d, R%2.2d", pc, mnemo, reg[0], reg[1])
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when "MOVC|Ri|R", "MOVX|Ri|R"
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vhdl_trans_list[pc] = instr_rr(opcode, reg[1], reg[0]);
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vhdl_tcl_list[pc] = tcl_bits_rr(pc, opcode, reg[1], reg[0])
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minstr_comment = format("0x%3.3X: %s (R%2.2d), R%2.2d", pc, mnemo, reg[1], reg[0])
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when "MOVC|Ri|K", "MOVX|Ri|K", "COUT|Ri|K", "XOUT|Ri|K"
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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minstr_comment = format("0x%3.3X: %s (R%2.2d), 0x%2.2X", pc, mnemo, reg[0], kk)
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when "MOVC|R|Ki", "MOVX|R|Ki", "CIN|R|Ki", "XIN|R|Ki"
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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minstr_comment = format("0x%3.3X: %s R%2.2d, (0x%2.2X)", pc, mnemo, reg[0], kk)
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when "MOV|R|K", "SUB|R|K", "ADD|R|K", "AND|R|K", "OR|R|K", "XOR|R|K", "CMP|R|K"
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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minstr_comment = format("0x%3.3X: %s R%2.2d, 0x%2.2X", pc, mnemo, reg[0], kk)
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when "MOVC|Ki|R", "MOVC|Ki|R", "MOVX|Ki|R", "MOVX|Ki|R", "COUT|Ki|R", "XOUT|Ki|R"
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vhdl_trans_list[pc] = instr_kr(opcode, kk, reg[1]);
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vhdl_tcl_list[pc] = tcl_bits_kr(pc, opcode, kk, reg[1])
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minstr_comment = format("0x%3.3X: %s (0x%2.2X), R%2.2d", pc, mnemo, kk, reg[1])
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when "CALL|K", "JMP|K", "JNZ|K", "JZ|K","JNC|K", "JC|K", "JLT|K", "JGT|K", "JLE|K", "JGE|K", "JEQ|K", "JNE|K"
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vhdl_trans_list[pc] = instr_k(opcode, kk)
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vhdl_tcl_list[pc] = tcl_bits_k(pc, opcode, kk)
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minstr_comment = format("0x%3.3X: %s 0x%3.3X", pc, mnemo, kk)
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when "PUSH|R", "POP|R", "SHR|R", "SHL|R", "ROR|R", "ROL|R", "RORC|R", "ROLC|R"
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vhdl_trans_list[pc] = instr_r(opcode, reg[0])
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vhdl_tcl_list[pc] = tcl_bits_r(pc, opcode, reg[0])
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minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
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when "TST|R"
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kk = 0
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minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
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opcode = mnemo_list.rindex("CMP|R|K").to_i
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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when "INC|R"
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kk = 1
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minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
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opcode = mnemo_list.rindex("ADD|R|K").to_i
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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when "DEC|R"
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kk = 1
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minstr_comment = format("0x%3.3X: %s R%2.2d", pc, mnemo, reg[0])
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opcode = mnemo_list.rindex("SUB|R|K").to_i
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vhdl_trans_list[pc] = instr_rk(opcode, reg[0], kk);
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vhdl_tcl_list[pc] = tcl_bits_rk(pc, opcode, reg[0], kk)
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else
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STDERR.puts format("Error in line %d: Not yet implemented %s", instruct[0], format)
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error = true
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end
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if error
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num_errors += 1
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break
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end
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vhdl_comment_list[pc] = minstr_comment
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puts vhdl_trans_list[pc] + " -- " + minstr_comment
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pc += 1
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end
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# --------------------------------------------------------
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# Output ROM file
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# --------------------------------------------------------
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if num_errors == 0
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filename = format("rom_%s.vhdl.snip", PROJECT_NAME)
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file = File.open(filename, "w")
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file.puts format("ENTITY %s IS\n", ENTITY_NAME)
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file.puts format("\tPort (\n")
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file.puts format("\tclk\t\t\t: in STD_LOGIC;\n")
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file.puts format("\tce\t\t\t: in STD_LOGIC;\n")
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file.puts format("\taddr\t\t: in %s;\n", ENTITY_ADDR_TYPE)
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file.puts format("\tdout\t\t: out %s\n", ENTITY_DATA_TYPE)
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file.puts format("\t);\n")
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file.puts format("END %s;\n", ENTITY_NAME)
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file.puts format("\n")
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file.puts format("ARCHITECTURE %s OF %s IS \n", PROJECT_NAME, ENTITY_NAME)
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file.puts format("\n")
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file.puts format("\ttype instruction_rom_t is array (0 to %d) of %s;\n", pc-1, ENTITY_DATA_TYPE)
|
|
file.puts format("\n")
|
|
file.puts format("\tconstant instruction_rom : instruction_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..pc-2)
|
|
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
|
end;
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
|
file.puts format("\t);\n")
|
|
file.puts format("\n")
|
|
file.puts format("begin")
|
|
file.puts format("\n")
|
|
file.puts format("PROM_READ:")
|
|
file.puts format("\tprocess(clk, ce)\n")
|
|
file.puts format("\tbegin\n")
|
|
file.puts format("\t\tif rising_edge(clk) and ce = '1' then\n")
|
|
file.puts format("\t\t\tdout <= instruction_rom(to_integer(addr));\n")
|
|
file.puts format("\t\tend if;\n")
|
|
file.puts format("\tend process;\n")
|
|
file.puts format("\n")
|
|
file.puts format("end %s;\n", PROJECT_NAME)
|
|
puts format("ROM file written to \"%s\"\n",filename)
|
|
file.close
|
|
end
|
|
if num_errors == 0
|
|
|
|
filename = format("preinit_%s.vhdl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
|
|
file.puts format("\tsignal instruction_rom : instruction_rom_t :=\n")
|
|
file.puts format("\t(\n");
|
|
for i in (0..pc-2)
|
|
file.puts "\t\t" + vhdl_trans_list[i] + ", -- " + vhdl_comment_list[i] + "\n"
|
|
end;
|
|
if pc < (MAX_SIZE_ROM-1)
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + ", -- " + vhdl_comment_list[pc-1] + "\n"
|
|
for i in (pc..(MAX_SIZE_ROM-2))
|
|
file.puts "\t\t" + instr(0) + ",\n"
|
|
end;
|
|
file.puts "\t\t" + instr(0) + "\n"
|
|
else
|
|
file.puts "\t\t" + vhdl_trans_list[pc-1] + " -- " + vhdl_comment_list[pc-1] + "\n"
|
|
end
|
|
file.puts format("\t);\n")
|
|
puts format("PREINIT file written to \"%s\"\n",filename)
|
|
file.close
|
|
end
|
|
if num_errors == 0
|
|
filename = format("rom_%s.tcl.snip", PROJECT_NAME)
|
|
file = File.open(filename, "w")
|
|
for i in (0..pc-1)
|
|
# Chipscope 8.1
|
|
# file.puts format("jtag_shiftdr $handle -buffer \"%s\" -endstate RTI -device $devid", vhdl_tcl_list[i].reverse);
|
|
|
|
# Chipscope 9.1
|
|
file.puts format("\# %s", vhdl_comment_list[i])
|
|
file.puts format("::chipscope::csejtag_tap shift_device_dr $handle $devid $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 %d \"%8.8X\"\n\n", vhdl_tcl_list[i].length, vhdl_tcl_list[i].to_i(2));
|
|
end;
|
|
puts format("TCL snippet written to \"%s\"\n",filename)
|
|
file.close
|
|
end
|
|
|
|
# --------------------------------------------------------
|
|
# Output final statistics
|
|
# --------------------------------------------------------
|
|
if num_errors == 0
|
|
puts "Program uses #{pc} instruction addresses"
|
|
puts "No errors found"
|
|
exit 0
|
|
else
|
|
puts "#{num_errors} errors found"
|
|
exit 1
|
|
end
|