jens
599726a7b2
git-svn-id: http://moon:8086/svn/vhdl/trunk@1531 cc03376c-175c-47c8-b038-4cd826a8556b
265 lines
6.6 KiB
VHDL
265 lines
6.6 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/JBUS/src/busmaster_async.vhd,v 1.1 2013/07/21 09:21:30 jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.utils_pkg.all;
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use work.busmaster_types.all;
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------------------------------------------------------------------
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entity busmaster_async is
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Generic
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(
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DATA_WIDTH : natural := 32;
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FIFO_DEPTH : natural := 4
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);
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Port
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(
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clk : in std_logic;
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rst : in std_logic;
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cmd_cycle_finished : out std_logic;
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cmd_cycle_en : in std_logic;
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cmd_rdy : out std_logic;
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cmd_we : in std_logic;
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cmd_in : in bm_cmd_t;
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din : in unsigned(DATA_WIDTH-1 downto 0);
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din_rdy : out std_logic;
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din_we : in std_logic;
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dout : out unsigned(DATA_WIDTH-1 downto 0);
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dout_vld : out std_logic;
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dout_re : in std_logic;
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-- J-BUS signals
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in std_logic;
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SRDY_I : in std_logic;
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MDAT_I : in unsigned(DATA_WIDTH-1 downto 0);
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MDAT_O : out unsigned(DATA_WIDTH-1 downto 0);
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ADDR_O : out unsigned(31 downto 0);
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SEL_O : out unsigned(DATA_WIDTH/8-1 downto 0);
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WE_O : out std_logic;
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CYC_O : out std_logic;
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STB_O : out std_logic;
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MRDY_O : out std_logic
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);
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end busmaster_async;
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architecture Behavioral of busmaster_async is
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-- Bus Command FIFO
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signal cmd_fifo_din : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
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signal cmd_fifo_dout : unsigned(32+DATA_WIDTH/8+1-1 downto 0);
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signal cmd_fifo_re : std_logic;
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signal cmd_fifo_we : std_logic;
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signal cmd_fifo_full : std_logic;
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signal cmd_fifo_empty : std_logic;
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-- Bus Read FIFO
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signal read_fifo_re : std_logic;
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signal read_fifo_we : std_logic;
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signal read_fifo_full : std_logic;
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signal read_fifo_empty : std_logic;
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signal write_fifo_re : std_logic;
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signal write_fifo_we : std_logic;
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signal write_fifo_full : std_logic;
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signal write_fifo_empty : std_logic;
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signal cycle_busy : std_logic;
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signal cycle_active : std_logic;
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signal cmd_en : std_logic;
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signal cmd_read_en : std_logic;
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signal read_cnt : integer range 0 to 65535;
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signal write : std_logic;
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signal jbus_cycle_busy : std_logic;
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type debug_t is record
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read_cnt : integer range 0 to 65535;
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end record;
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signal debug : debug_t;
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begin
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cmd_en <= cmd_we and not cmd_fifo_full;
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cmd_read_en <= cmd_en and not cmd_in.rw;
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write <= cmd_fifo_dout(32+DATA_WIDTH/8);
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dout_vld <= not read_fifo_empty;
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MRDY_O <= not read_fifo_full;
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ADDR_O <= cmd_fifo_dout(31 downto 0);
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SEL_O <= cmd_fifo_dout(32+DATA_WIDTH/8-1 downto 32);
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WE_O <= write;
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cmd_fifo_din <= cmd_in.rw & cmd_in.sel & cmd_in.addr;
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cmd_rdy <= not cmd_fifo_full;
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din_rdy <= not write_fifo_full;
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cmd_fifo_we <= cmd_en;
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cmd_fifo_re <= SRDY_I and jbus_cycle_busy;
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read_fifo_we <= ACK_I and jbus_cycle_busy;
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read_fifo_re <= dout_re;
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write_fifo_we <= din_we;
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write_fifo_re <= SRDY_I and jbus_cycle_busy and write and not cmd_fifo_empty;
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STB_O <= not cmd_fifo_empty;
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-- J-Bus domain
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proc_JBUS_to_local_cmd_cycle_finished:
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process(clk)
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begin
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if rising_edge(clk) then
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cmd_cycle_finished <= not jbus_cycle_busy;
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end if;
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end process;
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proc_JBUS_cycle:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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jbus_cycle_busy <= cycle_busy or cycle_active;
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CYC_O <= cycle_busy or cycle_active or cmd_we;
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end if;
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end process;
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proc_bus_read_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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read_cnt <= 0;
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elsif cmd_read_en = '1' and read_fifo_empty = '1' then
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read_cnt <= read_cnt + 1;
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elsif cmd_read_en = '0' and read_fifo_empty = '0' and dout_re = '1' then
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read_cnt <= read_cnt - 1;
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end if;
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end if;
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end process;
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debug_bus_read_counter:
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process(CLK_I)
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variable rd_en : std_logic;
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begin
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if rising_edge(CLK_I) then
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rd_en := not cmd_fifo_empty and cmd_fifo_re;
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if RST_I = '1' then
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debug.read_cnt <= 0;
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elsif read_fifo_we = '0' and rd_en = '1' then
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if write = '0' then
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debug.read_cnt <= debug.read_cnt + 1;
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end if;
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elsif read_fifo_we = '1' and rd_en = '0' then
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if read_fifo_full = '0' then
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debug.read_cnt <= debug.read_cnt - 1;
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end if;
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end if;
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end if;
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end process;
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proc_cycle_active:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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cycle_busy <= '0';
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elsif cycle_active = '1' and cmd_fifo_empty = '0' then
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cycle_busy <= '1';
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elsif cycle_active = '0' then
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cycle_busy <= '0';
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end if;
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end if;
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end process;
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proc_cycle_busy:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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cycle_active <= '0';
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elsif cycle_busy = '0' then
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if cmd_we = '1' then
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cycle_active <= '1';
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end if;
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elsif debug.read_cnt = 0 and write_fifo_empty = '1' and cmd_fifo_empty = '1' then
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cycle_active <= '0';
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end if;
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end if;
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end process;
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-- Bus READ FIFO
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inst_BM_READ_FIFO: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(FIFO_DEPTH),
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data_width => DATA_WIDTH,
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do_last_read_update => true
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)
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PORT MAP
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(
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rst => rst,
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clk_r => clk,
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clk_w => CLK_I,
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we => read_fifo_we,
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re => read_fifo_re,
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fifo_full => read_fifo_full,
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fifo_empty => read_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_r => dout,
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data_w => MDAT_I
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);
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-- Bus WRITE FIFO
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inst_BM_WRITE_FIFO: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(FIFO_DEPTH),
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data_width => DATA_WIDTH,
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do_last_read_update => false
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)
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PORT MAP
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(
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rst => rst,
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clk_r => CLK_I,
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clk_w => clk,
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we => write_fifo_we,
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re => write_fifo_re,
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fifo_full => write_fifo_full,
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fifo_empty => write_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_r => MDAT_O,
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data_w => din
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);
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-- Bus command FIFO
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inst_BM_CMD_FIFO: entity work.fifo_async
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GENERIC MAP
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(
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addr_width => NextExpBaseTwo(FIFO_DEPTH),
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data_width => cmd_fifo_din'length,
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do_last_read_update => false
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)
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PORT MAP
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(
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rst => rst,
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clk_r => CLK_I,
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clk_w => clk,
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we => cmd_fifo_we,
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re => cmd_fifo_re,
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fifo_full => cmd_fifo_full,
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fifo_empty => cmd_fifo_empty,
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fifo_afull => open,
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fifo_aempty => open,
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data_r => cmd_fifo_dout,
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data_w => cmd_fifo_din
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);
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end Behavioral;
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