jens
bdb8fec295
git-svn-id: http://moon:8086/svn/vhdl/trunk@1424 cc03376c-175c-47c8-b038-4cd826a8556b
49 lines
1.9 KiB
Plaintext
49 lines
1.9 KiB
Plaintext
This directory contains the source files for the DLX model suite.
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The following copyright holds:
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-- Copyright (C) 1993, Peter J. Ashenden
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-- Mail: Dept. Computer Science
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-- University of Adelaide, SA 5005, Australia
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-- e-mail: petera@cs.adelaide.edu.au
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 1, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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This suite is distributed as is, with no documentation or support. If
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I get time, I may provide documentation at a later date.
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Included in the directory is a file called module-directory, that
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lists the source files with a brief description of each. You should
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be able to compile them in the order listed.
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To run a simulation that includes the memory entity, you will need to
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have a file called dlx.out in the current working directory. This is
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the memory image file loaded by the memory entity, containing DLX
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instructions and data. The distribution directory contains two sample
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DLX programs, simple.s and test_loop.s, along with assembled versions
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in simple.out and test_loop.out. You can copy one of the .out files
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to dlx.out to run the simulation.
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I would be pleased to hear comments or bug reports (ie, bugs in the
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model, not bugs in your VHDL tools!). You can mail them to me at the
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above e-mail address.
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Have fun!
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Peter A.
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2 November 1993.
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