jens
012623b603
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123 lines
2.7 KiB
VHDL
123 lines
2.7 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:52:44 10/26/05
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-- Design Name:
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-- Module Name: ps2_phy - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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---- Uncomment the following library declaration if instantiating
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---- any Xilinx primitives in this code.
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library UNISIM;
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use UNISIM.VComponents.all;
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entity ps2_phy is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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ps2_clk : inout std_logic;
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ps2_data : inout std_logic;
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rx_clk : out std_logic;
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rx_data : out std_logic;
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tx_clk : in std_logic;
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tx_data : in std_logic
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);
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end ps2_phy;
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architecture Behavioral of ps2_phy is
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COMPONENT debounce
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GENERIC (ncyc_latency : integer);
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PORT
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(
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rst : IN std_logic;
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clk : IN std_logic;
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input : IN std_logic;
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output : OUT std_logic
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);
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END COMPONENT;
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signal clk_in : std_logic;
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signal data_in : std_logic;
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begin
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Inst_debounce_clk: debounce
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GENERIC MAP
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(
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ncyc_latency => 8
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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input => clk_in,
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output => rx_clk
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);
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Inst_debounce_data: debounce
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GENERIC MAP
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(
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ncyc_latency => 8
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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input => data_in,
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output => rx_data
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);
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IOBUF_inst_ps2_clk : IOBUF
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generic map
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(
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DRIVE => 2,
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
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IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
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IOSTANDARD => "DEFAULT",
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SLEW => "SLOW"
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)
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port map
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(
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O => clk_in, -- Buffer output
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IO => ps2_clk, -- Buffer inout port (connect directly to top-level port)
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I => tx_clk, -- Buffer input
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T => tx_clk -- 3-state enable input
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);
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IOBUF_inst_ps2_data : IOBUF
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generic map
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(
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DRIVE => 2,
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IBUF_DELAY_VALUE => "0", -- Specify the amount of added input delay for buffer, "0"-"16" (Spartan-3E only)
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IFD_DELAY_VALUE => "AUTO", -- Specify the amount of added delay for input register, "AUTO", "0"-"8" (Spartan-3E only)
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IOSTANDARD => "DEFAULT",
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SLEW => "SLOW"
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)
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port map
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(
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O => data_in, -- Buffer output
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IO => ps2_data, -- Buffer inout port (connect directly to top-level port)
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I => tx_data, -- Buffer input
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T => tx_data -- 3-state enable input
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);
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end Behavioral;
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