vhdl/lib/emac/src/emac_rx.vhd

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
use std.textio.all; --  Imports the standard textio package.

use work.emac_types.all;
use work.utils_pkg.all;

ENTITY emac_rx IS
	Generic
	(
		f_sysclk		: real		:= 100.0;
		RAM_SIZE		: natural	:= 2048
	);
	Port
	(
		clk				: in  STD_LOGIC;
		rst				: in  STD_LOGIC;
		dout_vld		: out STD_LOGIC;
		dout			: out unsigned(31 downto 0);
		ctrl_in			: in  rx_ctrl_in_t;
		ctrl_out		: out rx_ctrl_out_t;
		mii_rx_clk		: in  STD_LOGIC;
		mii_rx_dv		: in  STD_LOGIC;
		mii_rx_er		: in  STD_LOGIC;
		mii_rx			: in  unsigned(7 downto 0);
		mii_crs			: in  STD_LOGIC;
		mii_col			: in  STD_LOGIC
		
	);
END emac_rx;

ARCHITECTURE behavior OF emac_rx IS

	constant RAM_ADDR_WIDTH	: natural := NextExpBaseTwo(RAM_SIZE);
	
	subtype word_ptr_t is unsigned(RAM_ADDR_WIDTH-1 downto 0);
	
	-- Signals for EMAC connections
	signal cmd_fifo_din		: unsigned(2*word_ptr_t'length+2 downto 0);
	signal cmd_fifo_dout	: unsigned(2*word_ptr_t'length+2 downto 0);
	signal cmd_fifo_we		: std_logic;
	signal cmd_fifo_re		: std_logic;
	signal cmd_fifo_empty	: std_logic;
	signal cmd_fifo_full	: std_logic;

	signal reset_en			: std_logic;
	
	signal host_ptr			: word_ptr_t;
	signal host_ram_limit	: word_ptr_t;
	signal host_ram_base	: word_ptr_t;

	signal commit_en		: std_logic;

	signal xfer_ram_limit	: word_ptr_t;
	signal xfer_ram_full	: std_logic;
	signal xfer_base		: word_ptr_t;
	signal xfer_ptr			: word_ptr_t;
	signal xfer_en			: std_logic;
	signal xfer_set			: std_logic;
	signal xfer_vld			: std_logic;
	signal xfer_promiscious	: std_logic;

	signal ram_en_a			: std_logic;
	signal ram_we_a			: std_logic;
	signal ram_addr_a		: word_ptr_t;
	signal ram_din_a		: unsigned(31 downto 0);
	signal ram_dout_b		: unsigned(31 downto 0);
	signal ram_en_b			: std_logic;
	signal ram_addr_b		: word_ptr_t;

	signal sipo32_din		: unsigned(7 downto 0);
	signal sipo32_din_vld	: std_logic;
	signal sipo32_dout		: unsigned(31 downto 0);
	signal sipo32_dout_be	: unsigned(3 downto 0);
	signal sipo32_dout_vld	: std_logic;
	signal sipo32_dout_en	: std_logic;
	signal sipo32_en		: std_logic;
	signal sipo32_rst		: std_logic;
	
	signal sipo8_dout		: unsigned(7 downto 0);
	signal sipo8_rst		: std_logic;
	signal sipo8_dout_vld	: std_logic;
	signal sipo8_dout_en	: std_logic;
	signal sipo8_en			: std_logic;
	
	signal byte_count_rst	: std_logic;
	signal byte_count		: word_ptr_t;

	signal reset_pipe		: unsigned(31 downto 0);

	signal preamble_en		: std_logic;
	signal preamble_rdy		: std_logic;
	signal preamble_bsy		: std_logic;
	signal preamble_OK		: std_logic;

	signal mac_chk_rdy		: std_logic;
	signal mac_chk_BC		: std_logic;
	signal mac_chk_OK		: std_logic;
	signal mac_chk_num_OK	: natural range 0 to 6;
	signal mac_chk_num_BC	: natural range 0 to 6;
	signal mac_chk_cnt		: natural range 0 to 5;
	signal mac_addr			: mac_addr_t;
	signal mac_chk_addr		: mac_addr_t;
	
	signal Gbps_en			: std_logic;
	signal fcs_chk_en		: std_logic;
	signal rx_en			: std_logic;
	
	signal fcs_vld			: std_logic;
	signal fcs_din_vld		: std_logic;
	signal fcs_din			: unsigned(7 downto 0);
	signal fcs				: unsigned(31 downto 0);
	signal fcs_chk_OK		: std_logic;

	type host_state_t is (host_init, host_flush, host_idle);
	signal host_s, host_sn : host_state_t;

	type xfer_state_t is (xfer_init, xfer_idle, xfer_preamble, xfer_setup, xfer_active, xfer_finish, xfer_commit);
	signal xfer_s, xfer_sn : xfer_state_t;

	alias cmd_mac_ok_in is cmd_fifo_din(cmd_fifo_din'left);
	alias cmd_bcast_in is cmd_fifo_din(cmd_fifo_din'left-1);
	alias cmd_pkt_valid_in is cmd_fifo_din(cmd_fifo_din'left-2);
	alias cmd_nbytes_in is cmd_fifo_din(word_ptr_t'length-1 downto 0);
	alias cmd_base_in is cmd_fifo_din(2*word_ptr_t'length-1 downto word_ptr_t'length);

	alias cmd_mac_ok_out is cmd_fifo_dout(cmd_fifo_dout'left);
	alias cmd_bcast_out is cmd_fifo_dout(cmd_fifo_dout'left-1);
	alias cmd_pkt_valid_out is cmd_fifo_dout(cmd_fifo_dout'left-2);
	alias cmd_nbytes_out is cmd_fifo_dout(word_ptr_t'length-1 downto 0);
	alias cmd_base_out is cmd_fifo_dout(2*word_ptr_t'length-1 downto word_ptr_t'length);

begin

	ctrl_out.rx_size		<= resize(cmd_nbytes_out, 16);
	ctrl_out.pkt_avail		<= not cmd_fifo_empty;
	ctrl_out.pkt_valid		<= cmd_pkt_valid_out;
	ctrl_out.pkt_bcast		<= cmd_bcast_out;
	ctrl_out.pkt_mac_match	<= cmd_mac_ok_out;
	ctrl_out.reset_busy		<= reset_en;
	
	dout					<= ram_dout_b;

	ram_en_b				<= '1';
	ram_addr_b				<= host_ptr;

	ram_en_a				<= '1';
	ram_din_a				<= sipo32_dout;
	ram_addr_a				<= xfer_ptr;
	ram_we_a				<= xfer_en and sipo32_dout_vld;
	
	xfer_vld				<= (mac_chk_OK or mac_chk_BC or xfer_promiscious) and (not fcs_chk_en or fcs_chk_OK);
	cmd_fifo_we				<= commit_en and xfer_vld;
	cmd_fifo_re				<= ctrl_in.pkt_free_en;

	cmd_pkt_valid_in		<= fcs_chk_OK;
	cmd_mac_ok_in			<= mac_chk_OK;
	cmd_bcast_in			<= mac_chk_BC;
	cmd_nbytes_in			<= byte_count;
	cmd_base_in				<= xfer_base;
	

	reset_en				<= reset_pipe(reset_pipe'left);
	
------------------------------------------------------------------
reset_gen:
	process(clk)
	begin
		if rising_edge(clk) then
			if rst = '1' or ctrl_in.reset = '1' then
				reset_pipe	<= (others => '1');
			else
				reset_pipe	<= reset_pipe(reset_pipe'left-1 downto 0) & '0';
			end if;
		end if;
	end process;	

------------------------------------------------------------------
-- Fill stuff
------------------------------------------------------------------
fill_pointer:
	process(clk)
	begin
		if rising_edge(clk) then
			dout_vld			<= ctrl_in.pkt_read_en;
			if ctrl_in.pkt_req_en = '1' then
				host_ptr		<= cmd_base_out;
			elsif ctrl_in.pkt_read_en = '1' then
				host_ptr		<= host_ptr + 1;
			end if;
		end if;
	end process;	

------------------------------------------------------------------
-- Transfer stuff
------------------------------------------------------------------
host2xfer_sync_register:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			xfer_promiscious	<= ctrl_in.promiscious;
			Gbps_en				<= ctrl_in.Gbps_en;
			fcs_chk_en			<= ctrl_in.fcs_chk_en;
			mac_addr			<= ctrl_in.mac_addr;
			xfer_ram_limit		<= host_ram_limit;
		end if;	
	end process;	

host_limit_register:
	process(clk)
	begin
		if rising_edge(clk) then
			host_ram_base	<= xfer_base;
			if cmd_fifo_empty = '1' then
				host_ram_limit	<= host_ram_base - 1;
			else
				host_ram_limit	<= cmd_base_out - 1;
			end if;
		end if;	
			
	end process;	

xfer_ram_full_detect:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if xfer_set = '1' or reset_en = '1' then
				xfer_ram_full	<= '0';
			elsif xfer_en = '1' and sipo32_dout_vld = '1' then
				if xfer_ptr = xfer_ram_limit then
					xfer_ram_full <= '1';
				end if;
			end if;
		end if;	
			
	end process;	

xfer_base_logic:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if reset_en = '1' then
				xfer_base		<= (others => '0');
			elsif commit_en = '1' and xfer_vld = '1' then
				xfer_base		<= xfer_ptr;
			end if;
		end if;
	end process;	

xfer_pointer:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if xfer_set = '1' then
				xfer_ptr		<= xfer_base;
			elsif xfer_en = '1' and sipo32_dout_vld = '1' then
				xfer_ptr		<= xfer_ptr + 1;
			end if;
		end if;	
			
	end process;	
	
------------------------------------------------------------------
byte_counter:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if byte_count_rst = '1' then
				if fcs_chk_en = '0' then
					byte_count		<= to_unsigned(0, RAM_ADDR_WIDTH);
				else
					byte_count		<= unsigned(to_signed(-4, RAM_ADDR_WIDTH));
				end if;
			elsif sipo32_en = '1' and sipo32_din_vld = '1' then
				byte_count		<= byte_count + 1;
			end if;
		end if;
	end process;	

preamble_sync_logic:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if preamble_en = '0' then
				preamble_rdy	<= '0';
				preamble_bsy	<= '0';
				preamble_OK		<= '0';
			elsif sipo32_din_vld = '1' then
				if preamble_bsy = '1' then
					if sipo32_din = X"D5" then
						preamble_OK		<= '1';
					end if;
				end if;
				if sipo32_din /= X"55" then
					preamble_bsy	<= '0';
					preamble_rdy	<= preamble_bsy;
				else
					preamble_bsy	<= '1';
				end if;
			end if;
		end if;
	end process;	

mac_check_logic:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if byte_count_rst = '1' then
				mac_chk_rdy			<= '0';
				mac_chk_OK			<= '0';
				mac_chk_BC			<= '0';
				mac_chk_cnt			<= 0;
				mac_chk_num_OK		<= 0;
				mac_chk_num_BC		<= 0;
				mac_chk_addr		<= mac_addr;
			elsif mac_chk_rdy = '1' then
				if mac_chk_num_OK = 6 then 
					mac_chk_OK	<= '1';
				end if;
				if mac_chk_num_BC = 6 then 
					mac_chk_BC	<= '1';
				end if;
			elsif sipo32_din_vld = '1' and sipo32_en = '1' then
				if sipo32_din = mac_chk_addr(mac_chk_cnt) then
					mac_chk_num_OK	<= mac_chk_num_OK + 1;
				end if;
				if sipo32_din = X"FF" then
					mac_chk_num_BC	<= mac_chk_num_BC + 1;
				end if;
				if mac_chk_cnt /= 5 then
					mac_chk_cnt			<= mac_chk_cnt + 1;
				else
					mac_chk_rdy			<= '1';
				end if;
			end if;
		end if;
	end process;	

------------------------------------------------------------------
xfer_state_next:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if reset_en = '1' then
				xfer_s	<= xfer_init;
			else
				xfer_s	<= xfer_sn;
			end if;
		end if;
	end process;	

xfer_state:
	process(xfer_s, rx_en, sipo32_dout_en, preamble_bsy, preamble_OK, xfer_ram_full)
	begin
	
		commit_en			<= '0';
		xfer_set			<= '0';
		xfer_en				<= '0';
		sipo32_rst			<= '0';
		sipo32_en			<= '0';
		byte_count_rst		<= '0';
		preamble_en			<= '0';

		xfer_sn				<= xfer_s;
		
		case xfer_s is
		
		when xfer_init =>
			sipo32_rst			<= '1';
			if rx_en = '0' then
				xfer_sn 			<= xfer_idle;
			end if;
			
		when xfer_idle =>
			preamble_en			<= rx_en;
			if preamble_bsy = '1' then
				xfer_sn 		<= xfer_preamble;
			end if;

		when xfer_preamble =>
			preamble_en		<= rx_en;
			byte_count_rst	<= preamble_bsy;
			sipo32_en	<= rx_en and not preamble_bsy;
			if preamble_bsy = '0' then
				xfer_sn 		<= xfer_init;
				if preamble_OK = '1' then
					xfer_sn 		<= xfer_setup;
				end if;
			end if;			
			
		when xfer_setup =>
			xfer_set			<= '1';
			sipo32_en			<= rx_en;
			xfer_en				<= sipo32_dout_en;
			xfer_sn 			<= xfer_active;
		
		when xfer_active =>
			xfer_en				<= sipo32_dout_en;
			sipo32_en			<= rx_en;
			if xfer_ram_full = '1' then
				xfer_sn 		<= xfer_init;
			elsif rx_en = '0' then
				xfer_sn 		<= xfer_finish;
			end if;

		when xfer_finish =>
			xfer_en				<= sipo32_dout_en;
			if sipo32_dout_en = '0' then
				xfer_sn 		<= xfer_commit;
			end if;

		when xfer_commit =>
			commit_en		<= '1';
			xfer_sn			<= xfer_init;

		when others => 
			xfer_sn			<= xfer_init;
		end case;

	end process;

------------------------------------------------------------------
-- Instantiate synchronous FIFO
inst_cmd_fifo: entity work.fifo_async
	GENERIC MAP
	(
		addr_width			=> NextExpBaseTwo(RAM_SIZE) - 4,	-- RAMSIZE(words)/MIN_PACKET_LEN(words)
		data_width			=> cmd_fifo_din'length,
		do_last_read_update	=> false
	)
	PORT MAP
	(
		rst			=>	reset_en,
		clk_w		=>	mii_rx_clk,
		clk_r		=>	clk,
		we			=>	cmd_fifo_we,
		re			=>	cmd_fifo_re,
		fifo_full	=>	cmd_fifo_full,
		fifo_empty	=>	cmd_fifo_empty,
		fifo_afull	=>	open,
		fifo_aempty	=>	open,
		data_w		=>  cmd_fifo_din,
		data_r		=>  cmd_fifo_dout
	);

inst_ram : entity work.dpram_1w1r
	GENERIC MAP 
	(
		addr_width	=> RAM_ADDR_WIDTH,
		data_width	=> 32
	)
	PORT MAP 
	(
		clka		=> mii_rx_clk,
		clkb		=> clk,
		en_a		=> ram_en_a,
		en_b		=> ram_en_b,
		we_a		=> ram_we_a,
		addr_a		=> ram_addr_a,
		addr_b		=> ram_addr_b,
		din_a		=> ram_din_a,
		dout_b		=> ram_dout_b
	);

inst_sipo32 : entity work.sipo
	GENERIC MAP
	(
		data_width_in	=> 8,
		data_width_out	=> 32,
		msb_first		=> true
	)
	PORT MAP
	(
		rst			=> sipo32_rst,
		clk			=> mii_rx_clk,
		din_vld		=> sipo32_din_vld,
		din_en		=> sipo32_en,
		din			=> sipo32_din,
		dout_be		=> sipo32_dout_be,
		dout_vld	=> sipo32_dout_vld,
		dout		=> sipo32_dout,
		dout_en		=> sipo32_dout_en
		
	);
	
inst_fcs: entity work.crc32
	GENERIC MAP
	(
		crc32_init		=> X"00000000"
	)
	PORT MAP
	(
		rst				=> byte_count_rst,
		clk				=> mii_rx_clk,
		din_vld			=> fcs_din_vld,
		din				=> fcs_din,
		crc32_vld		=> fcs_vld,
		crc32_out		=> fcs
		
	);
	
	fcs_din		<= sipo32_din;
	fcs_din_vld	<= sipo32_en and sipo32_din_vld;
	
fcs_chk_register:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if fcs_vld = '1' then
				fcs_chk_OK	<= '0';
				if fcs = X"2144DF1C" then
					fcs_chk_OK	<= '1';
				end if;
			end if;
		end if;	
	end process;	

mii_input_register:
	process(mii_rx_clk)
	begin
		if rising_edge(mii_rx_clk) then
			if Gbps_en = '1' then
				sipo32_din		<= mii_rx;
				sipo32_din_vld	<= not mii_rx_er;
				rx_en			<= mii_rx_dv;
			else
				sipo32_din		<= sipo8_dout;
				sipo32_din_vld	<= sipo8_dout_vld;
				rx_en			<= sipo8_dout_en;
			end if;			
		end if;	
	end process;	

inst_sipo_8bit : entity work.sipo
	GENERIC MAP
	(
		data_width_in	=> 4,
		data_width_out	=> 8,
		msb_first		=> false
	)
	PORT MAP
	(
		rst			=> sipo8_rst,
		clk			=> mii_rx_clk,
		din_vld		=> mii_rx_dv,
		din_en		=> mii_rx_dv,
		din			=> mii_rx(3 downto 0),
		dout_be		=> open,
		dout_vld	=> sipo8_dout_vld,
		dout		=> sipo8_dout,
		dout_en		=> sipo8_dout_en
		
	);
	
	sipo8_rst		<= reset_en or not (mii_rx_dv or sipo8_dout_en);
	sipo8_en		<= not mii_rx_er;
	
end behavior;