jens
9a188d8b8a
- use LSB first for UART - Uart_wb: added generic for default baudrate and fifo depth git-svn-id: http://moon:8086/svn/vhdl/trunk@1358 cc03376c-175c-47c8-b038-4cd826a8556b
127 lines
2.7 KiB
VHDL
127 lines
2.7 KiB
VHDL
-- UART Transmitter
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--
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-- Version : 1.00
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-- Version Date : 15 December 2016
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--
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------------------------------------------------------------------------------------
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--
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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--
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------------------------------------------------------------------------------------
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--
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-- Main Entity
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--
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entity juart_tx is
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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en_16_x_baud : in std_logic;
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Tx_complete : out std_logic;
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ser_out : out std_logic
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);
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end juart_tx;
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--
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------------------------------------------------------------------------------------
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--
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-- Start of Main Architecture
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--
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architecture behavior of juart_tx is
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--
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------------------------------------------------------------------------------------
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--
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------------------------------------------------------------------------------------
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--
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-- Signals used
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--
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------------------------------------------------------------------------------------
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--
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signal dinreg : unsigned (7 downto 0);
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signal shiftreg : unsigned (9 downto 0);
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signal busy : std_logic;
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signal start : std_logic;
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signal shift_enable : std_logic;
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signal shift_enable_count : unsigned (3 downto 0);
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signal bit_count : unsigned (3 downto 0);
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--
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--
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begin
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ser_out <= shiftreg(0);
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Tx_complete <= not busy;
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shift_enable_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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shift_enable <= '0';
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if rst = '1' then
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shift_enable_count <= (others => '1');
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elsif en_16_x_baud = '1' then
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if shift_enable_count = 0 then
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shift_enable <= '1';
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shift_enable_count <= (others => '1');
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else
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shift_enable_count <= shift_enable_count - 1;
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end if;
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end if;
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end if;
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end process;
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bit_counter:
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process(clk)
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begin
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if rising_edge(clk) then
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if start = '1' then
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bit_count <= to_unsigned(shiftreg'length-1, bit_count'length);
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elsif shift_enable = '1' then
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if not (bit_count = 0) then
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bit_count <= bit_count - 1;
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end if;
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end if;
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end if;
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end process;
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transmit:
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process(clk)
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begin
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if rising_edge(clk) then
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if rst = '1' then
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shiftreg <= (others => '1');
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busy <= '0';
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start <= '0';
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elsif busy = '0' then
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if we = '1' then
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busy <= '1';
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start <= '1';
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dinreg <= din;
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end if;
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elsif shift_enable = '1' then
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if start = '1' then
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start <= '0';
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shiftreg <= '1' & dinreg & '0';
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elsif bit_count /= 0 then
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shiftreg <= '1' & shiftreg(shiftreg'left downto 1);
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if bit_count = 1 then
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busy <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end behavior;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE
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--
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------------------------------------------------------------------------------------
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