jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
15 lines
393 B
Plaintext
15 lines
393 B
Plaintext
## NOTE: Do not edit this file.
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## Auto generated by Project Navigator for Post-Translate Simulation
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##
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vlib work
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## Compile Post-Translate Model
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vcom -explicit -93 "../eval_ac/netgen/synthesis/ac97_test_synthesis.vhd"
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vcom -explicit -93 "../src/tb_ac97_test.vhd"
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vsim -t 1ps -lib work tb_ac97_test
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do {tb_ac97_test.wdo}
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view wave
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view structure
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view signals
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run 200us
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## End
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