103 lines
2.3 KiB
VHDL
103 lines
2.3 KiB
VHDL
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:25:45 10/15/05
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-- Design Name:
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-- Module Name: vga_ctrl_core - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.vga_types.all;
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entity vga_timing is
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Generic
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(
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tsvga : vga_timespec_t := ts_vga_800_600_72
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);
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Port
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(
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sys_rst : in std_logic;
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vga_clk : in std_logic;
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vga_ce : in std_logic;
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sync_h : out std_logic;
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sync_v : out std_logic;
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scan_pos_h : out natural range 0 to tsvga.ts_h.ncyc_scan-1;
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scan_pos_v : out natural range 0 to tsvga.ts_v.ncyc_scan-1;
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is_scan_h : out std_logic;
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is_scan_v : out std_logic;
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scan_rdy_h : out std_logic;
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scan_rdy_v : out std_logic
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);
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end vga_timing;
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architecture Behavioral of vga_timing is
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---------------------------------------------------------------------------------------------
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signal is_scan_h_i : std_logic;
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signal is_scan_v_i : std_logic;
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signal scan_rdy_h_i : std_logic;
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signal scan_rdy_v_i : std_logic;
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signal sync_h_i : std_logic;
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signal sync_v_i : std_logic;
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---------------------------------------------------------------------------------------------
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begin
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is_scan_h <= is_scan_h_i;
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is_scan_v <= is_scan_v_i;
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scan_rdy_h <= scan_rdy_h_i;
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scan_rdy_v <= scan_rdy_v_i;
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sync_h <= sync_h_i;
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sync_v <= sync_v_i;
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---------------------------------------------------------------------------------------------
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inst_vga_sync_h: entity work.vga_sync
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GENERIC MAP
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(
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ts => tsvga.ts_h
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)
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PORT MAP
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(
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rst => sys_rst,
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clk => vga_clk,
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ce => vga_ce,
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pos => scan_pos_h,
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sync => sync_h_i,
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is_scan => is_scan_h_i,
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rdy_scan => scan_rdy_h_i
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);
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inst_vga_sync_v: entity work.vga_sync
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GENERIC MAP
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(
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ts => tsvga.ts_v
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)
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PORT MAP
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(
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rst => sys_rst,
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clk => vga_clk,
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ce => scan_rdy_h_i,
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pos => scan_pos_v,
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sync => sync_v_i,
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is_scan => is_scan_v_i,
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rdy_scan => scan_rdy_v_i
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);
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---------------------------------------------------------------------------------------------
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end Behavioral;
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