128 lines
2.7 KiB
VHDL
128 lines
2.7 KiB
VHDL
--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 11:15:39 10/21/05
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-- Design Name:
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-- Module Name: fsm_scan - Behavioral
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-- Project Name:
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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use work.vga_types.all;
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entity vga_sync is
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Generic
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(
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ts : scan_timespec_t := (4,2,1,3,'0')
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);
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Port
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(
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rst : in std_logic;
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clk : in std_logic;
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ce : in std_logic;
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pos : out natural range 0 to ts.ncyc_scan-1;
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sync : out std_logic;
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is_scan : out std_logic;
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rdy_scan : out std_logic
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);
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end vga_sync;
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architecture Behavioral of vga_sync is
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type timing_state_t is (st_init, st_scan, st_front, st_sync, st_back);
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-- Counter
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signal state, next_state : timing_state_t;
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signal count_srst : std_logic;
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signal count : natural range 0 to ts.ncyc_scan-1;
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begin
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pos <= count;
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---------------------------------------------------------------------------------------------
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counter:
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process (clk)
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begin
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if rising_edge(clk) then
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if ce = '1' then
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if count_srst = '1' then
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count <= 0;
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else
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count <= count + 1;
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end if;
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end if;
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end if;
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end process;
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---------------------------------------------------------------------------------------------
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SYNC_TIMING:
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process (state, count)
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begin
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count_srst <= '0';
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rdy_scan <= '0';
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is_scan <= '0';
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sync <= '0';
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next_state <= state; --default is to stay in current state
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case (state) is
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when st_init =>
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count_srst <= '1';
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next_state <= st_front;
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when st_front =>
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if count = ts.ncyc_porch_front - 1 then
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count_srst <= '1';
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next_state <= st_sync;
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end if;
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when st_sync =>
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sync <= '1';
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if count = ts.ncyc_sync_pulse - 1 then
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count_srst <= '1';
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next_state <= st_back;
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end if;
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when st_back =>
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if count = ts.ncyc_porch_back - 1 then
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count_srst <= '1';
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next_state <= st_scan;
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end if;
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when st_scan =>
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is_scan <= '1';
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if count = ts.ncyc_scan - 1 then
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count_srst <= '1';
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rdy_scan <= '1';
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next_state <= st_front;
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end if;
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when others =>
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next_state <= st_init;
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end case;
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end process;
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SYNC_TIMING_NEXT:
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process (rst, clk)
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begin
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if rst = '1' then
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state <= st_init;
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elsif rising_edge(clk) and ce = '1' then
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state <= next_state;
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end if;
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end process;
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---------------------------------------------------------------------------------------------
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end Behavioral;
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