jens
1d3ac60495
git-svn-id: http://moon:8086/svn/vhdl/trunk@1545 cc03376c-175c-47c8-b038-4cd826a8556b
107 lines
3.3 KiB
Makefile
107 lines
3.3 KiB
Makefile
# -----------------------------------------------------------
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include $(VHDL_HOME)/make/defs.mk
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# -----------------------------------------------------------
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include $(LIB_PATH)/CPUs/MIPS/ghdl/mips_core.inc
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include $(LIB_PATH)/FIFO/ghdl/fifo_sync.inc
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include $(LIB_PATH)/FIFO/ghdl/fifo_async.inc
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include $(LIB_PATH)/emac/ghdl/emac_jbus.inc
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# Configs
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SRCS += $(LIB_PATH)/misc/utils_pkg.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_const.vhd
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SRCS += $(LIB_PATH)/models/memory/sdram/mt46v16m16/mt46v16m16.vhd
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SRCS += ../src/sdram_config_sim.vhd
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# Clock Generator
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SRCS += ../src/clockgen.vhd
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# UART
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SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
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SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
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SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd
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# MIPS
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SRCS += $(MIPS_CORE_SRCS)
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# ROM
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#vcom -explicit -93 "Z:/work/repos/mips/src/bootloader/test.ROM.vhd"
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SRCS += ../src/bootloader_flash.ROM.vhd
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SRCS += $(LIB_PATH)/JBUS/memory/src/rom_wb.vhd
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# RAMS
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SRCS += $(LIB_PATH)/rams/sim/src/dpram_1w1r2c_ro.vhd
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# VGA
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SRCS += $(LIB_PATH)/VGA_ctrl/src/fonts/char_rom_c64.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_types.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/char_gen.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_sync.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_timing.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_backend.vhd
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SRCS += $(LIB_PATH)/VGA_ctrl/src/vga_frontend64.vhd
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# UART
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SRCS += $(LIB_PATH)/uart/src/uart_types.vhd
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SRCS += $(LIB_PATH)/uart/src/sim/uart.vhd
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SRCS += $(LIB_PATH)/uart/src/uart_wb.vhd
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# PS2
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SRCS += $(LIB_PATH)/ps2_port/src/debounce.vhd
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SRCS += $(LIB_PATH)/ps2_port/src/ps2_core.vhd
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SRCS += $(LIB_PATH)/ps2_port/src/ps2_phy_virtex.vhd
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SRCS += $(LIB_PATH)/ps2_port/src/ps2_wb.vhd
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# GPIO
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SRCS += $(LIB_PATH)/JBUS/gpio/src/gpio_wb.vhd
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# LCD
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SRCS += $(LIB_PATH)/misc/lcd_port.vhd
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# Async port
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SRCS += $(LIB_PATH)/JBUS/async_port/src/async_types.vhd
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SRCS += $(LIB_PATH)/JBUS/async_port/src/async_port_wb.vhd
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SRCS += ../src/async_defs_sim.vhd
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# Flash and USB
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SRCS += $(LIB_PATH)/JBUS/flash_port/src/flash_port_wb.vhd
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# Sync SRAM
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SRCS += $(LIB_PATH)/SSRAM/src/package_utility.vhd
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SRCS += $(LIB_PATH)/SSRAM/src/CY7C1354B.vhd
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SRCS += $(LIB_PATH)/SSRAM/src/ssram_port_wb.vhd
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# SDRAM
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_types.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_clk_virtex4.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ddr_phy_virtex4.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_cmd.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_top.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/sdram_ctrl_frontend_wb64.vhd
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SRCS += $(LIB_PATH)/SDRAM/ddr_sdr_v1_5/src/ctrl_ddr_wb64.vhd
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# AC-97
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SRCS += $(LIB_PATH)/misc/singleshot.vhd
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SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_out.vhd
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SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_in.vhd
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SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac_io.vhd
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SRCS += $(LIB_PATH)/ac97_ctrl/src/core/ac97_wb.vhd
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# Ethernet MAC
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SRCS += $(EMAC_JBUS_SRCS)
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# Top and TB
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SRCS += ../src/mips_sys_sim.vhd
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SRCS += ../src/tb_mips_sys.vhd
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# Compile
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TARGET := tb_mips_sys
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ENTITY = tb_mips_sys
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RUN_TIME := 10ms
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WITH_VCD := y
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GHDL_OPTS := -P$(ROOT_PATH)/Common/sim/build/unisim/unisim -fsynopsys -fexplicit
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include $(VHDL_HOME)/make/ghdl.mk
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