71 lines
1.8 KiB
VHDL
71 lines
1.8 KiB
VHDL
--------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Programm counter
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.numeric_std.ALL;
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use work.cpu_pkg.all;
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entity pc is
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Port (
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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inc : in STD_LOGIC;
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load : in STD_LOGIC;
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pc_in : in inst_addr_t;
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pc_out : out inst_addr_t;
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pc_next : out inst_addr_t
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);
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end pc;
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architecture Behavioral of pc is
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begin
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proc_pc:
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process(rst, clk, inc, load, pc_in)
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variable vpc, vpc_reg: inst_addr_t;
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begin
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if rst = '1' then
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vpc_reg := (others => '0');
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elsif rising_edge(clk) then
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if inc = '1' or load = '1' then
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vpc_reg := vpc;
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elsif inc = '0' then
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pc_next <= vpc;
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end if;
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end if;
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if load = '1' then
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vpc := pc_in;
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else
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vpc := vpc_reg + 1;
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end if;
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pc_out <= vpc_reg;
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end process;
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end Behavioral;
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