vhdl/projects/mips_de0_nano/quartus/mips/tb_mips_sys.vhd

-------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: Testbench for JCPU
--            also writes 'opc.lst' for JASM-assembler
--
-- Copyright (C) 2007 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

LIBRARY ieee;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.numeric_std.ALL;

library work;
use work.mips_types.all;
use work.sdram_types.all;
use work.sdram_config.all;

ENTITY tb_mips_sys IS
END tb_mips_sys;

ARCHITECTURE behavior OF tb_mips_sys IS 

	constant CLK_PERIOD 			: time := 20 ns;
	
	signal debug				: unsigned(1 downto 0);

	-- Master 
	signal nmi_n					: STD_LOGIC := '1';
	signal rst_n					: STD_LOGIC := '0';
	signal clk						: STD_LOGIC := '0';

	-- SDRAM signals
	signal sdram_clk				: STD_LOGIC;
	signal sdram_cke				: STD_LOGIC;
	signal sdram_cs_n				: STD_LOGIC;
	signal sdram_cas_n				: STD_LOGIC;
	signal sdram_ras_n				: STD_LOGIC;
	signal sdram_we_n				: STD_LOGIC;
	signal sdram_addr				: sdr_addr_t;
	signal sdram_ba					: sdr_ba_t;
	signal sdram_dqm				: unsigned(PART_DM_WIDTH-1 downto 0);
	signal sdram_data				: unsigned(PART_DATA_WIDTH-1 downto 0);

	signal spi_ss_n					: std_logic;
	signal spi_clk					: std_logic;
	signal spi_miso					: std_logic := '1';
	signal spi_mosi					: std_logic;

	signal leds						: unsigned(7 downto 0);
	
BEGIN

------------------------------------------------------------------
CLK_GEN: process
	begin
		wait for CLK_PERIOD/2;
		clk <= not clk;
	end process;

------------------------------------------------------------------
uut : entity work.mips_sys
	PORT MAP
	(
		sys_nmi_n			=> nmi_n,
		sys_rst_n			=> rst_n,
		sys_clk				=> clk,
		
		sys_sdram_clk		=> sdram_clk,
		sys_sdram_cke		=> sdram_cke,
		sys_sdram_cs_n		=> sdram_cs_n,
		sys_sdram_cas_n		=> sdram_cas_n,
		sys_sdram_ras_n		=> sdram_ras_n,
		sys_sdram_we_n		=> sdram_we_n,
		sys_sdram_addr		=> sdram_addr,
		sys_sdram_ba		=> sdram_ba,
		sys_sdram_dqm		=> sdram_dqm,
		sys_sdram_data		=> sdram_data,

		spi_ss_n			=> spi_ss_n,
		spi_clk				=> spi_clk,
		spi_miso			=> spi_miso,
		spi_mosi			=> spi_mosi,
		
		sys_leds			=> leds
	);

------------------------------------------------------------------
   -- MICRON DDR SDRAM Simulation Model
   -- 4M x16x4 Banks
   -- IS42S16160B-7
i_mt48lc16m16_0 : entity work.mt48lc16m16a2 
      generic map
      (
        tAC       =>  6.5 ns,
        tHZ       =>  5.4 ns,
        tOH       =>  2.7 ns,
        tMRD      =>  2,     -- 2 Clk Cycles
        tRAS      => 45.0 ns,
        tRC       => 67.5 ns,
        tRCD      => 20.0 ns,
        tRP       => 20.0 ns,
        tRRD      => 14.0 ns,
        tAH       => 0.8 ns,
        tAS       => 1.5 ns,
        tCH       => 0.8 ns,
        tCL       => 2.5 ns,
        tCK       => 10.0 ns,
        tDH       => 0.8 ns,
        tDS       => 1.5 ns,
        tCKH      => 0.8 ns,
        tCKS      => 1.5 ns,
        tCMH      => 0.8 ns,
        tCMS      => 1.5 ns
      )
      port map
      (
         unsigned(Dq)	=> std_logic_vector(sdram_data),
         Addr  			=> std_logic_vector(sdram_addr),
         Ba   			=> std_logic_vector(sdram_ba),
         Clk  			=> sdram_clk,
         Cke   			=> sdram_cke,
         Cs_n  			=> sdram_cs_n,
         Ras_n 			=> sdram_ras_n,
         Cas_n 			=> sdram_cas_n,
         We_n  			=> sdram_we_n,
         Dqm    		=> std_logic_vector(sdram_dqm)
	);

inst_spi_flash: entity work.S25fl064k
	GENERIC MAP
	(	
		UserPreload		=> TRUE,
		mem_file_name	=> "dhry.elf.mem",
		screg_file_name	=> "none"
		
	)
    PORT MAP (
        SCK             => spi_clk, -- serial clock input
        SI              => spi_mosi,    -- serial data input
        CSNeg           => spi_ss_n,   -- chip select input
        SO              => spi_miso     -- SO
    );

------------------------------------------------------------------
STIMULUS: process

	begin


		wait for 3*CLK_PERIOD;
		wait until rising_edge(clk);
		rst_n <= '1';
		wait until rising_edge(clk);

		wait; 
	
	end process;
	
END;