jens
755b318e7a
git-svn-id: http://moon:8086/svn/vhdl/trunk@132 cc03376c-175c-47c8-b038-4cd826a8556b
50 lines
2.5 KiB
Plaintext
50 lines
2.5 KiB
Plaintext
vhdl work "W:\vhdl\projects\mips_sys\src\sdram_config.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_types.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_ctrl_pkg.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_sync.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_types.vhd"
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vhdl work "W:\vhdl\lib\misc\utils_pkg.vhd"
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vhdl work "W:\vhdl\lib\misc\singleshot.vhd"
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vhdl work "W:\vhdl\lib\misc\dpram_1w1r.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\sync_fifo_ctrl.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\gray_counter.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_timing.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\fonts\char_rom_fixedsys_8x16.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\clkgen_virtex4.vhd"
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vhdl work "W:\vhdl\lib\uart\kcuart_tx.vhd"
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vhdl work "W:\vhdl\lib\uart\kcuart_rx.vhd"
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vhdl work "W:\vhdl\lib\uart\bbfifo_16x8.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_cmd.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\reset_virtex4.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\ddr_phy_virtex4.vhd"
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vhdl work "W:\vhdl\lib\misc\dpram_2w2r_virtex4.vhd"
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vhdl work "W:\vhdl\lib\misc\dpram_1w1r_dist.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\async_fifo_ctrl.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_out.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_in.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\sys_types.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\ram_ld.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\bootloader.ROM_ld.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_backend.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\char_gen.vhd"
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vhdl work "W:\vhdl\lib\uart\uart_tx.vhd"
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vhdl work "W:\vhdl\lib\uart\uart_rx.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_top.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_sync_dist.vhd"
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vhdl work "W:\vhdl\lib\FIFO\src\fifo_async.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac_io.vhd"
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vhdl work "W:\vhdl\lib\VGA_ctrl\src\vga_frontend64.vhd"
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vhdl work "W:\vhdl\lib\uart\uart_wb.vhd"
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vhdl work "W:\vhdl\lib\SDRAM\ddr_sdr_v1_5\src\sdram_ctrl_frontend64_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\rom_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\ram_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\lcd_port.vhd"
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vhdl work "W:\vhdl\lib\misc\gpio_wb.vhd"
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vhdl work "W:\vhdl\lib\misc\clockgen_virtex4.vhd"
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vhdl work "W:\vhdl\lib\misc\async_port_wb.vhd"
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vhdl work "W:\vhdl\lib\CPUs\MIPS\src\core\mips_types.vhd"
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vhdl work "W:\vhdl\lib\ac97_ctrl\src\core\ac97_wb.vhd"
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vhdl work "W:\vhdl\projects\mips_sys\src\mips_sys.vhd"
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