83 lines
1.9 KiB
VHDL
83 lines
1.9 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
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-- This file: Testbench for JCPU
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-- also writes 'opc.lst' for JASM-assembler
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--
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-- Copyright (C) 2007 J. Ahrensfeld
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--
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-- This program is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, either version 3 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program. If not, see <http://www.gnu.org/licenses/>.
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--
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-- For questions and ideas, please contact the author at jens@jayfield.org
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--
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--------------------------------------------------------------------------
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LIBRARY ieee;
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use IEEE.STD_LOGIC_1164.ALL;
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USE ieee.numeric_std.ALL;
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use std.textio.all; -- Imports the standard textio package.
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library work;
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use work.mips_types.all;
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ENTITY tb_mips_embedded IS
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END tb_mips_embedded;
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ARCHITECTURE behavior OF tb_mips_embedded IS
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COMPONENT mips_embedded
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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halt : in STD_LOGIC;
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dout : out word_t
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);
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END COMPONENT;
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constant CLK_PERIOD : time := 10 ns;
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signal rst : std_logic := '1';
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signal clk : std_logic := '1';
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signal halt : std_logic := '0';
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signal dout : word_t;
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BEGIN
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uut: mips_embedded
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PORT MAP(
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rst => rst,
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clk => clk,
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halt => halt,
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dout => dout
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);
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CLK_GEN: process
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begin
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wait for CLK_PERIOD/2;
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clk <= not clk;
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end process;
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STIMULUS: process
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begin
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wait for 3*CLK_PERIOD;
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wait until rising_edge(clk);
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rst <= '0';
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wait;
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end process;
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END;
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