jens
6a1d8f729f
git-svn-id: http://moon:8086/svn/vhdl/trunk@234 cc03376c-175c-47c8-b038-4cd826a8556b
63 lines
1.3 KiB
VHDL
63 lines
1.3 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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entity signed_mult is
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generic
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(
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latency : natural := 2;
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data_width : natural := 16
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);
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port
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(
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clk : in std_logic;
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ce : in std_logic;
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a : in signed (data_width-1 downto 0);
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b : in signed (data_width-1 downto 0);
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result : out signed (2*data_width-1 downto 0)
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);
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end signed_mult;
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architecture rtl of signed_mult is
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constant in_latency : natural := latency - 1;
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constant out_latency : natural := latency - in_latency;
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subtype in_t is signed (data_width-1 downto 0);
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subtype out_t is signed (2*data_width-1 downto 0);
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type in_pipe_t is array (in_latency downto 1) of in_t;
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type out_pipe_t is array (out_latency downto 1) of out_t;
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signal a_pipe : in_pipe_t;
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signal b_pipe : in_pipe_t;
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signal out_pipe : out_pipe_t;
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begin
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result <= out_pipe(out_latency);
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input_pipe_reg:
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process(clk)
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begin
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if rising_edge(clk) then
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if ce = '1' then
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a_pipe <= a_pipe(in_latency-1 downto 1) & a;
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b_pipe <= b_pipe(in_latency-1 downto 1) & b;
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end if;
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end if;
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end process;
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mult_pipe_reg:
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process (clk)
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variable res : out_t;
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begin
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if rising_edge(clk) then
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res := a_pipe(in_latency) * b_pipe(in_latency);
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if ce = '1' then
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out_pipe <= out_pipe(out_latency-1 downto 1) & res;
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end if;
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end if;
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end process;
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end rtl;
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