jens
eafe4bf00d
git-svn-id: http://moon:8086/svn/vhdl/trunk@1329 cc03376c-175c-47c8-b038-4cd826a8556b
105 lines
2.4 KiB
VHDL
105 lines
2.4 KiB
VHDL
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--------------------------------------------------------------------------------
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-- Company:
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-- Engineer:
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--
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-- Create Date: 20:01:25 05/22/2007
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-- Design Name: eval_fixed_ja
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-- Module Name: H:/vhdl/projects/eval_fixed_ja/ise/tb_eval_fixed_ja.vhd
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-- Project Name: eval_fixed
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-- Target Device:
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-- Tool versions:
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-- Description:
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--
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-- VHDL Test Bench Created by ISE for module: eval_fixed_ja
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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-- Notes:
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-- This testbench has been automatically generated using types std_logic and
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-- std_logic_vector for the ports of the unit under test. Xilinx recommends
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-- that these types always be used for the top-level I/O of a design in order
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-- to guarantee that the testbench will bind correctly to the post-implementation
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-- simulation model.
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--------------------------------------------------------------------------------
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LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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USE ieee.std_logic_unsigned.all;
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USE ieee.numeric_std.ALL;
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ENTITY tb_eval_fixed_ja_vhd IS
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END tb_eval_fixed_ja_vhd;
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ARCHITECTURE behavior OF tb_eval_fixed_ja_vhd IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT eval_fixed_ja
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PORT(
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srst : IN std_logic;
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clk : IN std_logic;
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di1 : IN std_logic_vector(7 downto 0);
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di2 : IN std_logic_vector(7 downto 0);
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in_valid : IN std_logic;
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do : OUT std_logic_vector(7 downto 0);
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out_valid : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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SIGNAL srst : std_logic := '1';
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SIGNAL clk : std_logic := '0';
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SIGNAL in_valid : std_logic := '0';
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SIGNAL di1 : std_logic_vector(7 downto 0) := (others=>'0');
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SIGNAL di2 : std_logic_vector(7 downto 0) := (others=>'0');
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--Outputs
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SIGNAL do : std_logic_vector(7 downto 0);
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SIGNAL out_valid : std_logic;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: eval_fixed_ja PORT MAP(
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srst => srst,
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clk => clk,
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di1 => di1,
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di2 => di2,
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in_valid => in_valid,
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do => do,
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out_valid => out_valid
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);
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clk_gen : PROCESS
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BEGIN
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wait for 10 ns;
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clk <= not clk;
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END PROCESS;
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tb : PROCESS
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BEGIN
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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srst <= '0';
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di1 <= X"40";
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di2 <= X"20";
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wait for 20 ns;
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wait until rising_edge(clk);
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in_valid <= '1';
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wait until rising_edge(clk);
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in_valid <= '0';
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wait for 20 ns;
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-- Place stimulus here
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wait; -- will wait forever
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END PROCESS;
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END;
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