jens
d0c4a3d800
git-svn-id: http://moon:8086/svn/vhdl/trunk@1425 cc03376c-175c-47c8-b038-4cd826a8556b
336 lines
9.2 KiB
Verilog
336 lines
9.2 KiB
Verilog
/* PC.V
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**
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** This core adheres to GNU Public Licence
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** Jeung Joon Lee *** www.cmosexod.com
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** joon.lee@quantum.com
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**
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** JJL 12/12/98
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** updated 3/16/2000
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**
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** Highest module for the 8 bit general purpose microprocessor
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** Two submodules are declerared here, popcorn.v and sequencer.v
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** The role and functions of these modules are as following:
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** PC.V wrapper, and clock generator. Provides to the submodules
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** sys_clk and phase_1_clk
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** POPCORN.V The 8 bit datapath. Contains the ALU, register file,
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** the program counter, stack pointer and all of the muxes.
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** SEQUENCER.V The sequencer state machine. BAsed on the fetched opcode,
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** generates all of the sequence of control signals to
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** fetch more operands or finish executing the opcode.
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**
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*/
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`include "inc.h"
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module pc( sys_clk,
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sys_rst,
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addx_bus,
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data_bus,
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code_cs_l,
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code_rd_l,
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code_wr_l,
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sram_cs_l,
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slow_clk,
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port
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`ifdef show_debug_pins
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,
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w_opl,
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w_pc,
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w_oplo,
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state,
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w_acc,
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w_ax,
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w_bx,
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w_p,
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w_ophi,
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w_flag,
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phase_1_clk,
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slow_clk4,
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reg_flag,
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tst_bus,
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reg_acc,
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reg_ax,
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reg_bx,
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reg_p,
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reg_opl
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`endif
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);
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parameter N=6;
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input sys_clk;
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input sys_rst;
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inout [7:0] data_bus;
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inout [7:0] port;
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//input [1:0] tst_bus_sel;
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output [11:0] addx_bus;
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//output [7:0] tst_bus;
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output code_cs_l, code_rd_l, code_wr_l, sram_cs_l;
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output slow_clk;
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`ifdef show_debug_pins
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// DEBUG SIGNALS
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output w_opl;
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output w_pc;
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output w_oplo;
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output [3:0] state;
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output w_acc;
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output w_ax;
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output w_bx;
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output w_p;
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output w_ophi;
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output w_flag;
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output phase_1_clk;
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output slow_clk4;
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output [2:0] reg_flag;
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output tst_bus;
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output [7:0] reg_acc;
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output [7:0] reg_ax;
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output [7:0] reg_bx;
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output [7:0] reg_p;
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output [7:0] reg_opl;
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`endif
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wire w_acc,w_ax,w_bx,w_p,w_flag;
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wire pc_mux,w_pc,w_oplo,w_ophi,w_opl;
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wire slow_clk4;
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wire [2:0] bbus_mux;
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wire [3:0] alu_func;
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wire [2:0] reg_flag;
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wire [7:0] port;
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reg [1:0] state_slow_clk4;
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reg phase_1_clk;
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wire xx,slow_clk;
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wire [5:0] state;
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wire [7:0] b_bus,c_bus;
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wire [11:0] d_bus;
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wire [7:0] tst_bus;
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wire sp_mux, w_sp;
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wire [1:0] addx_mux;
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wire data_bus_wr;
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wire sram_cs_l, code_wr_l;
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wire flag_mux;
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wire [7:0] reg_acc;
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wire [7:0] reg_ax;
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wire [7:0] reg_bx;
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wire [7:0] reg_p;
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wire [7:0] reg_opl;
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//wire [7:0] port_in;
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//wire port_bus_ena;
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// define test bus
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/*
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always @(tst_bus_sel or reg_opl or c_bus or b_bus or d_bus)
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case (tst_bus_sel)
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2'b00: tst_bus <= reg_opl;
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//2'b01: tst_bus <= b_bus;
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default: tst_bus <= b_bus;
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//2'b10: tst_bus <= c_bus;
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//default: tst_bus <= c_bus;
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//2'b11: tst_bus <= d_bus;
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endcase
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*/
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//assign tst_bus=tst_bus_sel[0] ? b_bus : c_bus;
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assign tst_bus=c_bus;
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`ifdef use_clock_divider
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//
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// CLOCK DIVIDER
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//
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//
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// N=5 sets for 1Mhz operation
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// N=7 sets for 250Khz op. good for slow speed debug
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reg [N-1:0] clk;
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always @(posedge sys_clk or negedge sys_rst)
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if (~sys_rst) clk <=0;
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else clk <= clk + 1;
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assign slow_clk = clk[N-1];
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assign slow_clk4 = ~clk[N-3];
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`else
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reg [1:0] clk;
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always @(posedge sys_clk or negedge sys_rst)
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if (~sys_rst) clk <= 2'b00;
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else clk <= clk + 1;
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assign slow_clk = clk[1];
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assign slow_clk4 = sys_clk;
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`endif
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/* define phase_1 clock
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** | |
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** | ___ ___ ___ ___ | ___ ___
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** slow_clk*4 |/ \___/ \___/ \___/ \___|/ \___/ \___
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** | _______ _______ | _______
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** slow_clk*2 |/ \_______/ \_______|/ \_______
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** | _______________ | _______________
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** slow_clk |/ \_______________|/
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** |________ _______|_
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** phase_1 | \_______________/ |
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** | |
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*/
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always @(posedge slow_clk4 or negedge sys_rst)
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if (~sys_rst) begin
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state_slow_clk4<=2'b00;
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phase_1_clk<=1'b1;
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end
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else case (state_slow_clk4)
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2'b00: begin state_slow_clk4<=2'b01; phase_1_clk<=1'b1; end
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2'b01: begin state_slow_clk4<=2'b11; phase_1_clk<=1'b1; end
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2'b11: begin state_slow_clk4<=2'b10; phase_1_clk<=1'b0; end
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2'b10: begin state_slow_clk4<=2'b00; phase_1_clk<=1'b0; end
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endcase
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// instantiate the datapath
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popcorn POPCORN( .sys_clk(slow_clk),
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.sys_rst(sys_rst),
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.w_acc(w_acc),
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.w_ax(w_ax),
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.w_bx(w_bx),
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.w_p(w_p),
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.w_flag(w_flag),
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.bbus_mux(bbus_mux),
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.alu_func(alu_func),
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.pc_mux(pc_mux),
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.sp_mux(sp_mux),
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.flag_mux(flag_mux),
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.addx_mux(addx_mux),
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.w_pc(w_pc),
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.w_sp(w_sp),
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.w_oplo(w_oplo),
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.w_ophi(w_ophi),
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.w_opl(w_opl),
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.data_bus(data_bus),
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.port(port),
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// .port_in(port_in),
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.addx_bus(addx_bus),
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.reg_opl(reg_opl),
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.reg_flag(reg_flag),
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.b_bus(b_bus),
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.c_bus(c_bus),
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.d_bus(d_bus),
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.data_bus_wr(data_bus_wr),
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.code_wr_l(code_wr_l),
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.reg_acc(reg_acc),
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.reg_ax(reg_ax),
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.reg_bx(reg_bx),
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.reg_p(reg_p)
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);
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// instantiate the sequencer
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sequencer SEQ ( .sys_clk(slow_clk),
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.phase_1_clk(phase_1_clk),
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.sys_rst(sys_rst),
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.w_acc(w_acc),
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.w_ax(w_ax),
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.w_bx(w_bx),
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.w_p(w_p),
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.w_flag(w_flag),
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.bbus_mux(bbus_mux),
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.alu_func(alu_func),
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.pc_mux(pc_mux),
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.addx_mux(addx_mux),
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.sp_mux(sp_mux),
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.flag_mux(flag_mux),
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.w_pc(w_pc),
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.w_sp(w_sp),
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.w_oplo(w_oplo),
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.w_ophi(w_ophi),
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.w_opl(w_opl),
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.reg_opl(reg_opl),
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.code_cs_l(code_cs_l),
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.code_rd_l(code_rd_l),
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.code_wr_l(code_wr_l),
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.sram_cs_l(sram_cs_l),
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.reg_flag(reg_flag),
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.data_bus_wr(data_bus_wr),
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.next_state(state)
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);
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endmodule
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/*
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** Note on pin assignment:
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** o use pin file : "finalpin.pin"
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** o use global clock Y0 for 66Mhz source
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** o use global reset for reset.
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** o use N=6. This requires 64Mhz to give internal clock speed of 1Mhz.
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**
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** 2/12/99
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** o Fixed the LDM ACC,xx bug. ALU was not being set for c_bus = b_bus.
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** Call this 'popcorn - final'
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**
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** 2/11/99
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** o Uncovered and fixed 2 bugs relating the IO PORT:
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** 1.The signals 'reg_port_gate' which controls the gate of the port
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** output buffer has the wrong polarity. This was causing the port
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** to drive the port IO pin only when it was being read.
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** 2.The state of the bbus_mux[2:0] during LDACC/STADD was set to unknown.
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** This was causing the reg_port_gate to be deasserted during LDACC PORT
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** or STACC PORT instructions for 1 cycle, causing glitches in the IO port
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** pin
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**
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** 1/8/99
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** o Succesfully ran a timer program which toggles all bits of the
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** port register at 2mS interval (period=4mS). The program uses
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** an instrunctions timed 2mS delay subroutine.
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**
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** 1/7/99
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** o Somewhat final version. The test bus (TST[7:0]) has been dropped
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** and PORT[7:0] been used. All instructions works at least at 2 Mhz.
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** Call this 'popcorn -v5'
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**
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** 1/5/99
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** o Droppped the automatic pushing and popping of the flags when CALL/RET
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** are executed, (could not fit). So reduced the size of REG_OPHI down
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** to 4 from 8 bits. Instead the pushing of the flag is now done with
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** LDACC flag
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** LDM flag, #addx
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** PUSH flag
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** POP flag
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** instructions. The flag register still is muxed from ALU and c_bus.
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** Thanks Lord.
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** All that remains now is implementation of interrupt support.
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**
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** 1/3/99
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** o Removed DX and CX register from the register file, to free-up
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** the b_mux. The freed b_bus mux inputs are used by the PC (hi and low).
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** This allows PC to be pushed into the stack as well as CALL and RET
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** and push flag instructions
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**
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** 1/1/99
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** o Removed 7 level-deep hardware stack - it was obvious that this is not
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** a very robust way of having a stack. It limits the CALL/RET depth.
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** However my initial rational for not implementing the SP was that I
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** did not wanted to have a SRAM for stack. SRAM automatically implies
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** an extenal IC (since on FPGA you could not provide the required
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** amount of space).
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** o Added another addressing mode: direct mode, and 2 instructions: LDM and
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** STM (load mem, store mem). This brings the modes
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** to: register direct, immediate and direct.
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** Why not, I had decided to have exnal SRAM, so let's make use of it
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**
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** 12/28/98
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** o Added 7-level deep hardware LIFO to implement pushacc/popacc
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** instructions
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** o Implemented pushacc and popacc instructions in the sequencer.v
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**
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** 12/27/98
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** o Fixed a number of bugs, including CMPACC (reg direct) and ALU ops (reg
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** direct) being decoded as same.
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**
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** 12/26/98
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** o Shortenend the PC to 12 bits from 16, to reduce design size.
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** o REduced the datapath width to 8 from 16, to reduce design size.
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**
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** Lots of previous history not accounted for. Started to work on POPCORN
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** about 12/12/98
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*/
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