Files
vhdl/lib/JBUS/sim/tb_ram_wb.fdo
T
jens 0f36365c8f - refactored
git-svn-id: http://moon:8086/svn/vhdl/trunk@1526 cc03376c-175c-47c8-b038-4cd826a8556b
2021-03-24 17:00:28 +00:00

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## NOTE: Do not edit this file.
##
vlib work
# Top and TB
vcom -explicit -93 "../utils_pkg.vhd"
vcom -explicit -93 "../../rams/dpram_1w1r1c_ra_sim.vhd"
vcom -explicit -93 "../ram_wb.vhd"
vcom -explicit -93 "../tb_ram_wb.vhd"
vsim -t 1ps -lib work tb_ram_wb
do {tb_ram_wb.wdo}
view wave
view structure
view signals
run 1.5us