jens
e3aeadebf5
git-svn-id: http://moon:8086/svn/vhdl/trunk@1420 cc03376c-175c-47c8-b038-4cd826a8556b
56 lines
2.1 KiB
Plaintext
56 lines
2.1 KiB
Plaintext
#
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# XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
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# SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
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# XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
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# AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
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# OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
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# IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
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# AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
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# FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
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# WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
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# IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
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# REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
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# INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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# FOR A PARTICULAR PURPOSE.
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#
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# (c) Copyright 2005 Xilinx, Inc.
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# All rights reserved.
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#
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# Bus clock nets
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NET "sys_clk" TNM_NET = "sys_clk";
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TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;
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NET sys_clk LOC = AE14;
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NET sys_clk IOSTANDARD = LVCMOS33;
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NET sys_rst_n LOC = D6;
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NET sys_rst_n PULLUP;
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NET sys_rst_n TIG;
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NET sys_rst_n IOSTANDARD = LVCMOS33;
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#------------------------------------------------------------------------------
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# IO Pad Location Constraints / Properties for Expansion Header GPIO
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#------------------------------------------------------------------------------
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#SMA Connectors
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NET clk_out_sma<0> LOC = C12; # SMA_IN_N
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NET clk_out_sma<1> LOC = C13; # SMA_IN_P
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NET clk_out_sma<2> LOC = D7; # SMA_OUT_N
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NET clk_out_sma<3> LOC = D8; # SMA_OUT_P
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NET clk_out_sma<*> IOSTANDARD = LVCMOS33;
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NET clk_out_sma<*> SLEW = FAST;
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NET clk_out_sma<*> DRIVE = 12;
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# Headers
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NET clk_out_bus<0> LOC = AF24; # HDR1_64
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NET clk_out_bus<1> LOC = AE24; # HDR1_62
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NET clk_out_bus<2> LOC = AD22; # HDR1_8
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NET clk_out_bus<3> LOC = AB21; # HDR1_58
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NET clk_out_bus<4> LOC = W20; # HDR1_44
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NET clk_out_bus<5> LOC = W21; # HDR1_48
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NET clk_out_bus<6> LOC = AB22; # HDR1_14
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NET clk_out_bus<7> LOC = AD25; # HDR1_20
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NET clk_out_bus<*> IOSTANDARD = LVCMOS33;
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NET clk_out_bus<*> SLEW = FAST;
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NET clk_out_bus<*> DRIVE = 12;
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