437 lines
11 KiB
VHDL
437 lines
11 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use IEEE.MATH_REAL.ALL;
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library work;
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use work.mips_types.all;
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ENTITY dcache IS
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Generic
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(
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cache_size : natural := 2048; -- words
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line_size : natural := 8 -- words
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);
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Port
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(
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RST_I : in STD_LOGIC;
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CLK_I : in STD_LOGIC;
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ACK_I : in STD_LOGIC;
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SRDY_I : in STD_LOGIC;
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ADDR_O : out word_t;
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DAT_I : in word_t;
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STB_O : out STD_LOGIC;
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CYC_O : out STD_LOGIC;
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en : in STD_LOGIC;
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cpu_en : in STD_LOGIC;
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cpu_we : in STD_LOGIC;
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cpu_be : in unsigned(3 downto 0);
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cpu_addr : in word_t;
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cpu_din : in word_t;
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cpu_dout : out word_t;
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cpu_busy : out STD_LOGIC
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);
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END dcache;
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ARCHITECTURE behavior OF dcache IS
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COMPONENT dpram_1w1r
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GENERIC
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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PORT (
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clka : in STD_LOGIC;
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clkb : in STD_LOGIC;
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en_a : in STD_LOGIC;
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en_b : in STD_LOGIC;
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we_a : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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END COMPONENT;
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COMPONENT dpram_2w2r is
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GENERIC
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(
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addr_width : integer := 3;
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data_width : integer := 8
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);
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PORT
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(
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clk_a : in STD_LOGIC;
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clk_b : in STD_LOGIC;
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en_a : in STD_LOGIC;
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en_b : in STD_LOGIC;
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we_a : in STD_LOGIC;
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we_b : in STD_LOGIC;
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addr_a : in unsigned (addr_width-1 downto 0);
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addr_b : in unsigned (addr_width-1 downto 0);
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din_a : in unsigned (data_width-1 downto 0);
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din_b : in unsigned (data_width-1 downto 0);
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dout_a : out unsigned (data_width-1 downto 0);
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dout_b : out unsigned (data_width-1 downto 0)
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);
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END COMPONENT;
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function lg2(x : natural) return natural is
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begin
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return natural(ceil(log2(real(x))));
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end lg2;
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function po2(x : natural) return natural is
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begin
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return 2**lg2(x);
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end po2;
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constant word_index_width : natural := lg2(line_size);
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constant cache_index_width : natural := lg2(cache_size) - word_index_width;
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constant tag_width : natural := 32 - word_index_width - cache_index_width - 2;
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constant tag_parity_width : natural := 3;
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constant tram_data_width : natural := 2 + tag_parity_width + tag_width;
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constant tram_addr_width : natural := cache_index_width;
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subtype tram_data_t is unsigned (tram_data_width-1 downto 0);
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type dcache_entry_t is record
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valid : std_logic;
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dirty : std_logic;
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tv_p : unsigned(tag_parity_width-1 downto 0);
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tag : unsigned(tag_width-1 downto 0);
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end record;
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alias cpu_word_index is cpu_addr(word_index_width+1 downto 2);
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alias cpu_cache_index is cpu_addr(cache_index_width+word_index_width+1 downto word_index_width+2);
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alias cpu_tag is cpu_addr(tag_width+cache_index_width+word_index_width+1 downto cache_index_width+word_index_width+2);
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function to_dcache_entry(x : tram_data_t) return dcache_entry_t is
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variable result : dcache_entry_t;
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begin
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result.valid := x(0);
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result.dirty := x(1);
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result.tv_p := x(4 downto 2);
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result.tag := x(tag_width+4 downto 5);
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return result;
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end to_dcache_entry;
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function to_tram_data(x : dcache_entry_t) return tram_data_t is
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variable result : tram_data_t;
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begin
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result(0) := x.valid;
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result(1) := x.dirty;
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result(4 downto 2) := x.tv_p;
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result(tag_width+4 downto 5) := x.tag;
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return result;
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end to_tram_data;
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type cache_state_t is (init, ready, flush, mem_request, mem_access, mem_wait, mem_data, upd_cache, rd_cache);
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signal s, sn : cache_state_t;
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signal cache_busy : std_logic;
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signal cache_hit : std_logic;
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signal tag_match : std_logic;
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signal word_index_reg : unsigned(word_index_width-1 downto 0);
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signal cache_index_reg : unsigned(cache_index_width-1 downto 0);
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signal tag_index_reg : unsigned(tag_width-1 downto 0);
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signal cache_entry_in : dcache_entry_t;
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signal cache_entry_out : dcache_entry_t;
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signal cpu_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
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signal cpu_dram_dout : word_t;
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signal cpu_dram_din : word_t;
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signal cpu_data_reg : word_t;
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signal cpu_be_reg : unsigned(3 downto 0);
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signal cpu_we_reg : std_logic;
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signal ctrl_dram_en : std_logic;
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signal ctrl_dram_addr : unsigned(lg2(cache_size)-1 downto 0);
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signal ctrl_dram_din : word_t;
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signal ctrl_dram_we : unsigned(3 downto 0);
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signal cpu_dram_we : unsigned(3 downto 0);
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signal cpu_dram_en : std_logic;
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signal cpu_en2 : std_logic;
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signal cpu_we2 : std_logic;
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signal tram_addr_rd : unsigned(cache_index_width-1 downto 0);
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signal tram_dout : tram_data_t;
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signal tram_addr_wr : unsigned(cache_index_width-1 downto 0);
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signal tram_din : tram_data_t;
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signal tram_re : std_logic;
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signal tram_we : std_logic;
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signal ram_index_count : natural range 0 to 2**word_index_width-1;
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signal ram_index_count_rst : std_logic;
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signal cache_index_count : natural range 0 to 2**cache_index_width-1;
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signal cache_index_count_en : std_logic;
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signal mem_index_count : natural range 0 to 2**word_index_width-1;
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signal mem_index_count_en : std_logic;
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signal mem_index_count_rst : std_logic;
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signal cpu_reg_en : std_logic;
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signal was_miss : std_logic;
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signal data_write : std_logic;
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signal cpu_hit_we : std_logic;
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signal instant_raw : std_logic;
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begin
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cpu_hit_we <= cpu_we2 and cache_hit;
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cpu_index_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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cache_index_reg <= (others => '0');
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tag_index_reg <= (others => '0');
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elsif cpu_reg_en = '1' and en = '1' and instant_raw = '0' then
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word_index_reg <= cpu_word_index;
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cache_index_reg <= cpu_cache_index;
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tag_index_reg <= cpu_tag;
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end if;
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end if;
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end process;
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cpu_data_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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cpu_we_reg <= '0';
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elsif cpu_reg_en = '1' and en = '1' then
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cpu_data_reg <= cpu_din;
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cpu_be_reg <= cpu_be;
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cpu_we_reg <= cpu_we;
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end if;
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end if;
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end process;
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cpu_was_wr_register:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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cpu_en2 <= '0';
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cpu_we2 <= '0';
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if cpu_en = '1' and en = '1' then
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cpu_we2 <= cpu_we;
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cpu_en2 <= '1';
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cpu_dram_din <= cpu_din;
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end if;
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end if;
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end process;
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instant_raw_logic:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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instant_raw <= cpu_hit_we and cpu_en and en and not cpu_we;
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end if;
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end process;
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inst_tag_ram : dpram_1w1r
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GENERIC MAP (
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addr_width => tram_addr_width,
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data_width => tram_data_width
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)
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PORT MAP (
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clka => CLK_I,
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clkb => CLK_I,
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en_a => '1',
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en_b => tram_re,
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we_a => tram_we,
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addr_a => tram_addr_wr,
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addr_b => tram_addr_rd,
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din_a => tram_din,
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dout_b => tram_dout
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);
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gen_data_ram:
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for i in 0 to 3 generate
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begin
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inst_data_ram : dpram_2w2r
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GENERIC MAP (
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addr_width => lg2(cache_size),
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data_width => word_t'length/4
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)
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PORT MAP (
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clk_a => CLK_I,
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clk_b => CLK_I,
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en_a => ctrl_dram_en,
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en_b => '1',
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we_a => ctrl_dram_we(i),
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we_b => cpu_dram_we(i),
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addr_a => ctrl_dram_addr,
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addr_b => cpu_dram_addr,
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din_a => ctrl_dram_din(8*(i+1)-1 downto 8*i),
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din_b => cpu_dram_din(8*(i+1)-1 downto 8*i),
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dout_a => open,
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dout_b => cpu_dram_dout(8*(i+1)-1 downto 8*i)
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);
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end generate;
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cache_state_next:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if RST_I = '1' then
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s <= init;
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else
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s <= sn;
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end if;
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end if;
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end process;
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cpu_busy <= cache_busy or instant_raw;
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cpu_dout <= cpu_dram_dout;
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tag_match <= '1' when tag_index_reg = cache_entry_out.tag else '0';
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cache_hit <= tag_match and cache_entry_out.valid;
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tram_din <= to_tram_data(cache_entry_in);
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tram_addr_rd <= cpu_cache_index when was_miss = '0' else cache_index_reg;
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cache_entry_out <= to_dcache_entry(tram_dout);
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cpu_dram_addr <= (cpu_cache_index & cpu_word_index) when (was_miss = '0' and cpu_hit_we = '0' and instant_raw = '0') else (cache_index_reg & word_index_reg);
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ADDR_O <= tag_index_reg & cache_index_reg & to_unsigned(mem_index_count, word_index_width) & "00";
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ctrl_dram_addr <= cache_index_reg & to_unsigned(ram_index_count, word_index_width);
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ctrl_dram_din <= DAT_I;
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ctrl_dram_we <= (others => '1');
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ctrl_dram_en <= data_write and ACK_I;
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cpu_dram_we <= cpu_be_reg when (cpu_hit_we = '1') else (others => '0');
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cache_state:
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process(s, instant_raw, cache_hit, cache_index_count, ram_index_count, mem_index_count, cache_index_reg, ACK_I, tag_index_reg, cpu_en, SRDY_I, cpu_en2, cpu_we_reg)
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begin
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cpu_reg_en <= '0';
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cache_busy <= '1';
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tram_we <= '0';
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cache_index_count_en <= '0';
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ram_index_count_rst <= '0';
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mem_index_count_en <= '0';
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mem_index_count_rst <= '0';
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CYC_O <= '0';
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STB_O <= '0';
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tram_re <= '0';
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was_miss <= '0';
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data_write <= '0';
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tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
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cache_entry_in.tv_p <= (others => '0');
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cache_entry_in.tag <= tag_index_reg;
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cache_entry_in.valid <= '0';
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cache_entry_in.dirty <= '0';
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sn <= s;
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case s is
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when init =>
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sn <= flush;
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when ready =>
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cache_busy <= '0';
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cpu_reg_en <= '1';
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tram_re <= cpu_en;
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if cpu_en2 = '1' then
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if cache_hit = '0' and cpu_we_reg = '0' then
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sn <= mem_request;
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cpu_reg_en <= '0';
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cache_busy <= '1';
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CYC_O <= '1';
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end if;
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end if;
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when flush =>
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cache_index_count_en <= '1';
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tram_addr_wr <= to_unsigned(cache_index_count, cache_index_width);
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tram_we <= '1';
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cache_entry_in.valid <= '0';
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cache_entry_in.tag <= (others => '0');
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if cache_index_count = 0 then
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sn <= ready;
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if cpu_en = '1' then
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cpu_reg_en <= '1';
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tram_re <= '1';
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end if;
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end if;
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when mem_request =>
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ram_index_count_rst <= '1';
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mem_index_count_rst <= '1';
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CYC_O <= '1';
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if SRDY_I = '1' then
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sn <= mem_access;
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end if;
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when mem_access =>
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data_write <= '1';
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mem_index_count_en <= '1';
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CYC_O <= '1';
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STB_O <= '1';
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if mem_index_count = 2**word_index_width-1 then
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if SRDY_I = '1' then
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sn <= mem_data;
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end if;
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end if;
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when mem_data =>
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CYC_O <= '1';
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data_write <= '1';
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if ram_index_count = 2**word_index_width-1 then
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if ACK_I = '1' then
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sn <= upd_cache;
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end if;
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end if;
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when upd_cache =>
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CYC_O <= '1';
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tram_addr_wr <= cache_index_reg;
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tram_we <= '1';
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cache_entry_in.valid <= '1';
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sn <= rd_cache;
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when rd_cache =>
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tram_re <= '1';
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was_miss <= '1';
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sn <= ready;
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when others =>
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sn <= ready;
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end case;
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end process;
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cache_index_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if cache_index_count_en = '0' then
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cache_index_count <= 2**cache_index_width-1;
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elsif cache_index_count /= 0 then
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cache_index_count <= cache_index_count - 1;
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end if;
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end if;
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end process;
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ram_index_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if ram_index_count_rst = '1' then
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ram_index_count <= 0;
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elsif data_write = '1' and ACK_I = '1' then
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if ram_index_count /= 2**word_index_width-1 then
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ram_index_count <= ram_index_count + 1;
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end if;
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end if;
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end if;
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end process;
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mem_index_counter:
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process(CLK_I)
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begin
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if rising_edge(CLK_I) then
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if mem_index_count_rst = '1' then
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mem_index_count <= 0;
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elsif mem_index_count_en = '1' and SRDY_I = '1' then
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if mem_index_count /= 2**word_index_width-1 then
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mem_index_count <= mem_index_count + 1;
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end if;
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end if;
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end if;
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end process;
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end behavior;
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