jens
13488ae71e
- ctrl is input git-svn-id: http://moon:8086/svn/vhdl/trunk@1241 cc03376c-175c-47c8-b038-4cd826a8556b
66 lines
1.3 KiB
VHDL
66 lines
1.3 KiB
VHDL
LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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LIBRARY WORK;
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USE WORK.uart_types.all;
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use std.textio.all; -- Imports the standard textio package.
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------------------------------------------------------------------------------------
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ENTITY uart IS
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Port
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(
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clk : in STD_LOGIC;
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rst : in STD_LOGIC;
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we : in STD_LOGIC;
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re : in STD_LOGIC;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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ser_rx : in std_logic;
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ser_tx : out std_logic;
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ctrl : in ctrl_t;
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status : out status_t
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);
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END uart;
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ARCHITECTURE simulation OF uart IS
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begin
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-- RX
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dout <= X"00";
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status.rx_present <= '0';
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-- TX
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ser_tx <= '1';
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status.tx_complete <= '1';
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status.tx_empty <= '1';
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status.tx_full <= '0';
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proc_tx:
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process(clk)
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file output: text open write_mode is "STD_OUTPUT";
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variable L : line;
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begin
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if rising_edge(clk) then
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if we = '1' then
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if din /= X"0D" then
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write(L, character'val(to_integer(din)));
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end if;
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if din = X"0A" then
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writeline(output, L);
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end if;
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end if;
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end if;
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end process;
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end simulation;
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------------------------------------------------------------------------------------
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--
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-- END OF FILE UART_RX.VHD
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--
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------------------------------------------------------------------------------------
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