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029bf8eb22a4f7a5e122062702e4b764480114e4
vhdl/lib/SDRAM/ddr_sdr_v1_5/sim
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History
jens 8a8adce98e - using now 64-bit SDR interface (2 SDRAMS) 
git-svn-id: http://moon:8086/svn/vhdl/trunk@74 cc03376c-175c-47c8-b038-4cd826a8556b
2008-10-18 13:31:15 +00:00
..
compile_simprim.do
Intital revision
2008-10-02 13:37:55 +00:00
compile_unisim.do
Intital revision
2008-10-02 13:37:55 +00:00
ModelSim SE .lnk
Intital revision
2008-10-02 13:37:55 +00:00
tb_sdram_ctrl_frontend_wb.fdo
- using now 64-bit SDR interface (2 SDRAMS)
2008-10-18 13:31:15 +00:00
tb_sdram_ctrl_frontend_wb.wdo
- using now 64-bit SDR interface (2 SDRAMS)
2008-10-18 13:31:15 +00:00