jens
67d79572d7
git-svn-id: http://moon:8086/svn/vhdl/trunk@1411 cc03376c-175c-47c8-b038-4cd826a8556b
62 lines
3.7 KiB
Plaintext
62 lines
3.7 KiB
Plaintext
# Copyright (C) 1991-2008 Altera Corporation
|
|
# Your use of Altera Corporation's design tools, logic functions
|
|
# and other software and tools, and its AMPP partner logic
|
|
# functions, and any output files from any of the foregoing
|
|
# (including device programming or simulation files), and any
|
|
# associated documentation or information are expressly subject
|
|
# to the terms and conditions of the Altera Program License
|
|
# Subscription Agreement, Altera MegaCore Function License
|
|
# Agreement, or other applicable license agreement, including,
|
|
# without limitation, that your use is for the sole purpose of
|
|
# programming logic devices manufactured by Altera and sold by
|
|
# Altera or its authorized distributors. Please refer to the
|
|
# applicable agreement for further details.
|
|
|
|
|
|
# The default values for assignments are stored in the file
|
|
# syn_fir_lowpass_assignment_defaults.qdf
|
|
# If this file doesn't exist, and for assignments not listed, see file
|
|
# assignment_defaults.qdf
|
|
|
|
# Altera recommends that you do not modify this file. This
|
|
# file is updated automatically by the Quartus II software
|
|
# and any changes you make may be lost or overwritten.
|
|
|
|
|
|
set_global_assignment -name FAMILY "Cyclone III"
|
|
set_global_assignment -name DEVICE EP3C25F324C6
|
|
set_global_assignment -name TOP_LEVEL_ENTITY syn_fir_lowpass
|
|
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
|
|
set_global_assignment -name PROJECT_CREATION_TIME_DATE "11:53:04 DECEMBER 31, 2008"
|
|
set_global_assignment -name LAST_QUARTUS_VERSION 8.1
|
|
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
|
|
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
|
|
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
|
|
set_global_assignment -name NOMINAL_CORE_SUPPLY_VOLTAGE 1.2V
|
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
|
|
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
|
|
set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
|
|
set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
|
|
set_global_assignment -name ENABLE_ADVANCED_IO_TIMING ON
|
|
set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
|
|
set_global_assignment -name DSP_BLOCK_BALANCING AUTO
|
|
set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
|
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
|
|
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
|
|
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
|
|
set_global_assignment -name SDC_FILE syn_fir_lowpass.out.sdc
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/misc/dpram_1w1r.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_semi_parallel.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/delay_line.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_pkg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../src/syn_fir_lowpass_sp.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/fir_stage_sys.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/misc/utils_pkg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/fixed_util_pkg.vhd
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/math_utility_pkg.vhdl
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/fixed/altera/fixed_pkg_c.vhdl
|
|
set_global_assignment -name VHDL_FILE ../../../../lib/filter/src/filter_pkg.vhd
|
|
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
|
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
|
set_global_assignment -name USE_CONFIGURATION_DEVICE OFF |