jens
70e48af3ab
git-svn-id: http://moon:8086/svn/vhdl/trunk@1036 cc03376c-175c-47c8-b038-4cd826a8556b
70 lines
1.7 KiB
VHDL
70 lines
1.7 KiB
VHDL
-----------------------------------------------------------------------
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-- $Header: D:\usr\cvsroot/VHDL/lib/misc/lcd_port.vhd,v 1.1 2008/08/23 08:20:29 Jens Exp $
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-----------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.NUMERIC_STD.ALL;
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------------------------------------------------------------------
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entity lcd_port is
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Port (
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rst : in std_logic;
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clk : in std_logic;
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we : in std_logic;
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din : in unsigned(7 downto 0);
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dout : out unsigned(7 downto 0);
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lcd_d : inout unsigned(3 downto 0);
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lcd_e : out std_logic;
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lcd_rs : out std_logic;
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lcd_rw : out std_logic
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);
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end lcd_port;
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architecture Behavioral of lcd_port is
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constant clcd_e : integer := 7;
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constant clcd_rs : integer := 6;
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constant clcd_rw : integer := 5;
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type lcd_t is record
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d : unsigned(3 downto 0);
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e : std_logic;
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rs : std_logic;
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rw : std_logic;
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end record;
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------------------------------------------------------------------
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begin
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proc_lcd_port:
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process(rst, clk)
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variable vlcd : lcd_t;
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begin
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if (rst = '1') then
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dout <= (others => '0');
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vlcd.d := (others => '0');
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vlcd.e := '0';
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vlcd.rw := '1';
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vlcd.rs := '0';
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elsif rising_edge(clk) then
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dout <= unsigned("0000" & lcd_d);
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if we = '1' then
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vlcd.d := din(3 downto 0);
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vlcd.e := din(clcd_e);
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vlcd.rs := din(clcd_rs);
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vlcd.rw := din(clcd_rw);
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end if;
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end if;
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if vlcd.rw = '0' then
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lcd_d <= unsigned(vlcd.d);
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else
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lcd_d <= (others => 'Z');
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end if;
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lcd_e <= vlcd.e;
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lcd_rs <= vlcd.rs;
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lcd_rw <= vlcd.rw;
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end process;
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------------------------------------------------------------------
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end Behavioral;
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