jens
b3da8c3d7b
Committed on the Free edition of March Hare Software CVSNT Server. Upgrade to CVS Suite for more features and support: http://march-hare.com/cvsnt/ git-svn-id: http://moon:8086/svn/vhdl/trunk@297 cc03376c-175c-47c8-b038-4cd826a8556b
118 lines
3.0 KiB
VHDL
118 lines
3.0 KiB
VHDL
-------------------------------------------------------------------------
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-- Project: JCPU, a portable 8-bit RISC CPU written in VHDL
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-- This file: Dual-ported register file with asynchrous read
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-- Copyright (C) 2007 J. Ahrensfeld
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-- This library is free software; you can redistribute it and/or
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-- modify it under the terms of the GNU Lesser General Public
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-- License as published by the Free Software Foundation; either
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-- version 2.1 of the License, or (at your option) any later version.
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-- This library is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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-- Lesser General Public License for more details.
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-- You should have received a copy of the GNU Lesser General Public
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-- License along with this library; if not, write to the Free Software
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-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
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-- For questions and ideas, please contact the author at jens@jayfield.org
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-----------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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use work.fifo_ctrl_pkg.all;
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entity fifo_sync_dist is
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Generic (
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addr_width : natural := 4;
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data_width : natural := 8;
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almost_full_thresh : integer := 12;
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almost_empty_thresh : integer := 4
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);
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Port
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(
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rst : in STD_LOGIC;
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clk : in STD_LOGIC;
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we : in STD_LOGIC;
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re : in STD_LOGIC;
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fifo_full : out STD_LOGIC;
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fifo_empty : out STD_LOGIC;
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fifo_afull : out STD_LOGIC;
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fifo_aempty : out STD_LOGIC;
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data_w : in unsigned (data_width-1 downto 0);
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data_r : out unsigned (data_width-1 downto 0)
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);
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end fifo_sync_dist;
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architecture Behavioral of fifo_sync_dist is
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signal mem_wr_en : STD_LOGIC;
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signal mem_rd_en : STD_LOGIC;
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signal ptr_w : unsigned (addr_width-1 downto 0);
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signal ptr_r : unsigned (addr_width-1 downto 0);
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signal full : STD_LOGIC;
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signal empty : STD_LOGIC;
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signal almost_full : STD_LOGIC;
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signal almost_empty : STD_LOGIC;
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signal pre_full : STD_LOGIC;
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signal pre_empty : STD_LOGIC;
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begin
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mem_wr_en <= not full;
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mem_rd_en <= not pre_empty;
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fifo_full <= full;
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fifo_empty <= empty;
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fifo_afull <= almost_full;
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fifo_aempty <= almost_empty;
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inst_fifo_sync_ctrl: entity work.fifo_sync_ctrl
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GENERIC MAP
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(
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addr_width => addr_width,
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almost_full_thresh => almost_full_thresh,
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almost_empty_thresh => almost_empty_thresh
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)
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PORT MAP
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(
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rst => rst,
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clk => clk,
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we => we,
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re => re,
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ptr_w => ptr_w,
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ptr_r => ptr_r,
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fifo_full => full,
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fifo_empty => empty,
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fifo_pre_full => pre_full,
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fifo_pre_empty => pre_empty,
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fifo_afull => almost_full,
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fifo_aempty => almost_empty
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);
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inst_dpram_1w1r: entity work.dpram_1w1r_dist
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GENERIC MAP (
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addr_width => addr_width,
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data_width => data_width
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)
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PORT MAP(
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clka => clk,
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clkb => clk,
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en_a => mem_wr_en,
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en_b => mem_rd_en,
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we_a => we,
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addr_a => ptr_w,
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addr_b => ptr_r,
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din_a => data_w,
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dout_b => data_r
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);
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end Behavioral;
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