include mips_core.inc
include ../../../../lib/FIFO/ghdl/fifo_sync.inc
include ../../../../lib/FIFO/ghdl/fifo_async.inc

# RAMS
SRCS += ../../../rams/sim/dpram_2w2r2c_ra.vhd
SRCS += ../../../rams/sim/dpram_1w1r2c_ra.vhd

# FIFOS
SRCS += $(FIFO_SYNC_SRCS)
SRCS += $(FIFO_ASYNC_SRCS)

# UART
SRCS += ../../../uart/src/uart_types.vhd
SRCS += ../../../uart/src/sim/uart.vhd
SRCS += ../../../uart/src/uart_wb.vhd

# GPIO
SRCS += ../../../misc/gpio_wb.vhd

# Async port
SRCS += ../../../misc/async_types.vhd
SRCS += ../../../misc/async_port_wb.vhd
SRCS += ../src/async_defs.vhd

# ROM
#SRCS += Z:/work/repos/mips/src/bootloader/build/ml402/eb/bootloader.elf.ROM.vhd
#SRCS += Z:/work/repos/mips/src/bootloader/build/denano/eb/bootloader.elf.ROM.vhd
SRCS += ../src/bootloader_flash.ROM.vhd
SRCS += ../../../misc/rom_wb.vhd

# MIPS
SRCS += $(MIPS_CORE_SRCS)

# TB
SRCS += ../src/tb_mips_top.vhd

# Compile
TARGET := tb_mips_top
ENTITY = tb_mips_top
RUN_TIME := 1500us
WITH_VCD := y

include ../../../../Common/make/ghdl.mk