#
#     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
#     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
#     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
#     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
#     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
#     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
#     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
#     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
#     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
#     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
#     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
#     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
#     FOR A PARTICULAR PURPOSE.
#     
#     (c) Copyright 2005 Xilinx, Inc.
#     All rights reserved.
#

# Bus clock nets
#NET sys_clk TNM_NET = "sys_clk";
#TIMESPEC "TSSYSCLK" = PERIOD "sys_clk" 9.9 ns HIGH 50 %;

NET sys_clk LOC = AE14;
NET sys_clk IOSTANDARD = LVCMOS33;
NET sys_rst_n LOC = D6;
NET sys_rst_n PULLUP;
NET sys_rst_n TIG;

# GPLED 0-3
NET sys_led<0>  LOC = G5;  #GPLED0
NET sys_led<1>  LOC = G6;  #GPLED1
NET sys_led<2>  LOC = A11; #GPLED2
NET sys_led<3>  LOC = A12; #GPLED3

#NET "led<*>" SLEW = SLOW;
#NET "led<*>" DRIVE = 2;


# Dip Switches 1-8
#NET sys_test_in<0> LOC = U24; # DIP SW 8
#NET sys_test_in<1> LOC = U25; # DIP SW 7
#NET sys_test_in<2> LOC = V23; # DIP SW 6
#NET sys_test_in<3> LOC = U23; # DIP SW 5
#NET sys_test_in<4> LOC = U26; # DIP SW 4
#NET sys_test_in<5> LOC = T26; # DIP SW 3
#NET sys_test_in<6> LOC = R19; # DIP SW 2
#NET sys_test_in<7> LOC = R20; # DIP SW 1
#NET sys_test_in<0> IOSTANDARD = LVCMOS33;
#NET sys_test_in<1> IOSTANDARD = LVCMOS33;
#NET sys_test_in<2> IOSTANDARD = LVCMOS33;
#NET sys_test_in<3> IOSTANDARD = LVCMOS33;
#NET sys_test_in<4> IOSTANDARD = LVCMOS33;
#NET sys_test_in<5> IOSTANDARD = LVCMOS33;
#NET sys_test_in<6> IOSTANDARD = LVCMOS33;
#NET sys_test_in<7> IOSTANDARD = LVCMOS33;

#NET "sys_test_in<*>" PULLDOWN;
#NET "sys_test_in<*>" TIG;
#NET "sys_test_in<*>" SLEW = SLOW;
#NET "sys_test_in<*>" DRIVE = 2;

NET sys_hpi_a<0>   LOC        = U22;
NET sys_hpi_a<1>   LOC        = Y10;
NET sys_hpi_a<*>   IOSTANDARD = LVCMOS33;
NET sys_hpi_a<*>   SLEW       = FAST;
NET sys_hpi_a<*>   DRIVE      = 8;
NET sys_hpi_d<0>   LOC        = AB7;
NET sys_hpi_d<1>   LOC        = AC9;
NET sys_hpi_d<2>   LOC        = AB9;
NET sys_hpi_d<3>   LOC        = AE6;
NET sys_hpi_d<4>   LOC        = AD6;
NET sys_hpi_d<5>   LOC        = AF9;
NET sys_hpi_d<6>   LOC        = AE9;
NET sys_hpi_d<7>   LOC        = AD8;
NET sys_hpi_d<8>   LOC        = AC8;
NET sys_hpi_d<9>   LOC        = AF4;
NET sys_hpi_d<10>  LOC        = AE4;
NET sys_hpi_d<11>  LOC        = AD3;
NET sys_hpi_d<12>  LOC        = AC3;
NET sys_hpi_d<13>  LOC        = AF6;
NET sys_hpi_d<14>  LOC        = AF5;
NET sys_hpi_d<15>  LOC        = AA7;
NET sys_hpi_d<*>   IOSTANDARD = LVCMOS33;
NET sys_hpi_d<*>   SLEW       = FAST;
NET sys_hpi_d<*>   DRIVE      = 8;
NET sys_hpi_d<*>   PULLUP;
NET sys_hpi_rd_n    LOC        = AA8;
NET sys_hpi_rd_n    IOSTANDARD = LVCMOS33;
NET sys_hpi_rd_n    SLEW       = FAST;
NET sys_hpi_rd_n    DRIVE      = 8;
NET sys_hpi_wr_n    LOC        = Y8;
NET sys_hpi_wr_n    IOSTANDARD = LVCMOS33;
NET sys_hpi_wr_n    SLEW       = FAST;
NET sys_hpi_wr_n    DRIVE      = 8;

NET sys_hpi_cs_n    LOC        = AF10;
NET sys_hpi_cs_n    IOSTANDARD = LVCMOS33;
NET sys_hpi_cs_n    SLEW       = FAST;
NET sys_hpi_cs_n    DRIVE      = 8;
NET sys_hpi_rst_n   LOC        = A7;
NET sys_hpi_rst_n   IOSTANDARD = LVCMOS25;
NET sys_hpi_rst_n   TIG;
NET sys_hpi_int     LOC        = V5;
NET sys_hpi_int     IOSTANDARD = LVCMOS33;
NET sys_hpi_int     TIG;
NET sys_hpi_int     PULLUP;

NET sys_sace_mpce_n       LOC        = AD5;
NET sys_sace_mpce_n       IOSTANDARD = LVCMOS33;
NET sys_sace_mpce_n       SLEW       = FAST;
NET sys_sace_mpce_n       DRIVE      = 8;