--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:16:42 13.05.2007
-- Design Name:   tb_nco
-- Module Name:   tb_nco.vhd
-- Project Name:  nco
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-----------------------------------------------------------------------
-- $Header: /tmp/cvsroot/VHDL/lib/FIFO/src/tb_async_fifo_ctrl.vhd,v 1.1 2008-08-23 08:20:28 Jens Exp $
-----------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.MATH_REAL.ALL;
USE IEEE.NUMERIC_STD.ALL;
USE STD.TEXTIO.ALL;

-- LIBRARY WORK;
-- USE.YOURLIB.WHATELSE

ENTITY tb_async_fifo_ctrl IS
END tb_async_fifo_ctrl;

ARCHITECTURE behavior OF tb_async_fifo_ctrl IS 

	--Constants
	constant PERIOD_W 	: time := 10 ns;
	constant PERIOD_R 	: time := 20 ns;
	constant ADDR_WIDTH : integer := 3;

	--Inputs
	signal rst					: STD_LOGIC := '1';
	signal clk_w				: STD_LOGIC := '0';
	signal clk_r				: STD_LOGIC := '0';
	signal we					: STD_LOGIC := '0';
	signal re					: STD_LOGIC := '0';
	signal din					: unsigned (7 downto 0);
	--Outputs

	signal ptr_w				: unsigned (ADDR_WIDTH-1 downto 0);
	signal ptr_r				: unsigned (ADDR_WIDTH-1 downto 0);
	signal dout					: unsigned (7 downto 0);
	signal fifo_full			: STD_LOGIC;
	signal fifo_empty			: STD_LOGIC;
	signal fifo_almost_full		: STD_LOGIC;
	signal fifo_almost_empty	: STD_LOGIC;
	signal mem_we				: STD_LOGIC;

	signal write_en				: STD_LOGIC := '0';
	signal read_en				: STD_LOGIC := '0';

	signal wdata				: unsigned (7 downto 0) := (others => '0');
	signal rdata				: unsigned (7 downto 0) := (others => '0');
	signal rdata2				: unsigned (7 downto 0) := (others => '0');

BEGIN

	din <= wdata;
	
	-- Instantiate the Unit Under Test (UUT)
	uut: entity work.async_fifo_ctrl
	GENERIC MAP
	(
		addr_width			=> ADDR_WIDTH,
		almost_full_thresh	=> 6,
		almost_empty_thresh	=> 2
	)
	PORT MAP
	(
		rst			=>	rst,
		clk_w		=>	clk_w,
		clk_r		=>	clk_r,
		we			=>	we,
		re			=>	re,
		ptr_w		=>	ptr_w,
		ptr_r		=>	ptr_r,
		fifo_full	=>	fifo_full,
		fifo_empty	=>	fifo_empty,
		fifo_afull	=>	fifo_almost_full,
		fifo_aempty	=>	fifo_almost_empty

	);

	inst_dpram: entity work.dpram
	GENERIC MAP (
		addr_width	=> ADDR_WIDTH,
		data_width	=> 8
	)
	PORT MAP(
		clka		=> clk_w,
		clkb		=> clk_r,
		en_a		=> '1',
		en_b		=> '1',
		we_a		=> mem_we,
		addr_a		=> ptr_w,
		addr_b		=> ptr_r,
		din_a		=> din,
		dout_b		=> dout
	);

 	tb_clk_w : PROCESS
	BEGIN
		clk_w <= not clk_w;
		wait for PERIOD_W/2;
	END PROCESS;

 	tb_clk_r : PROCESS
	BEGIN
		clk_r <= not clk_r;
		wait for PERIOD_R/2;
	END PROCESS;

 	tb_write : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 5*PERIOD_W;
		rst			<= '0';
		wait for 5*PERIOD_W;
		write_en <= '1';
		wait for 15*PERIOD_W;
		write_en <= '0';
		
		wait; 
		
	END PROCESS;

 	tb_read : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 15*PERIOD_R;
		read_en <= '1';
		
		wait; 
		
	END PROCESS;
	
	we <= write_en and not fifo_full;
	mem_we <= we;
	
 	tb_w : PROCESS(rst, clk_w)
	BEGIN

		if rst = '1' then
			wdata <= (others => '0');
		elsif rising_edge(clk_w) then
			if we = '1' then
				wdata <= wdata + 1;
			end if;				
		end if;	

	END PROCESS;
	
	re	<= read_en and not fifo_empty;
	
 	tb_r : PROCESS(rst, clk_r)
	BEGIN

		if rst = '1' then
			rdata <= (others => '0');
		elsif rising_edge(clk_r) then
			rdata2 <= rdata;
			if re = '1' then
				assert rdata2 = dout report "FIFO read error!" severity failure;
				rdata <= rdata + 1;
			end if;				
		end if;	
		
	END PROCESS;

END behavior;