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-- Company: 
-- Engineer:
--
-- Create Date:    18:45:29 10/22/05
-- Design Name:    
-- Module Name:    prescaler - Behavioral
-- Project Name:   
-- Target Device:  
-- Tool versions:  
-- Description:
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity prescaler is
	 Generic (divide : integer := 8);
    Port ( rst : in std_logic;
           clk : in std_logic;
           ce : in std_logic;
           rdy : out std_logic);
end prescaler;

architecture Behavioral of prescaler is

begin

proc_prescaler: process(rst, clk, ce)
variable cnt_prescaler : integer range 0 to divide-1;
begin
	if rst = '1' then
		cnt_prescaler := divide - 1;
		rdy <= '0';
	elsif clk'event and clk='1' then
		if ce = '1' then
			if cnt_prescaler = 0 then
				cnt_prescaler := divide - 1;
				rdy <= '1';
			else
				cnt_prescaler := cnt_prescaler - 1;
				rdy <= '0';
			end if;
		end if;
	end if;
end process proc_prescaler;

end Behavioral;