-------------------------------------------------------------------------
-- Project: Dual-Port RAM with 1 clock latency for simulation
-- This file: Dual-Port RAM 1 write, 1 read, 2 clocks, registered address

-- Copyright (C) 2007 J. Ahrensfeld

-- This library is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.

-- This library is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-- Lesser General Public License for more details.

-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the Free Software
-- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

-- For questions and ideas, please contact the author at jens@jayfield.org

-----------------------------------------------------------------------
-- $Header: D:\usr\cvsroot/VHDL/lib/rams/dpram_1w1r2c_ra_xil.vhd,v 1.1 2013/02/09 09:27:21 jens Exp $
-----------------------------------------------------------------------

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

entity dpram_x1w1r2c_ra is
	Generic 
	(
		addr_width_a : integer := 10;
		addr_width_b : integer := 10;
		data_width_a : integer := 32;
		data_width_b : integer := 32
	);
	Port
	(
		clk_a		: in  STD_LOGIC;
		clk_b		: in  STD_LOGIC;
		en_a		: in  STD_LOGIC;
		en_b		: in  STD_LOGIC;
		we_a		: in  STD_LOGIC;
		addr_a		: in  unsigned (addr_width_a-1 downto 0);
		addr_b		: in  unsigned (addr_width_b-1 downto 0);
		din_a		: in  unsigned (data_width_a-1 downto 0);
		dout_b		: out unsigned (data_width_b-1 downto 0)
	);
end dpram_x1w1r2c_ra;

architecture Behavioral of dpram_x1w1r2c_ra is

	constant NUM_RAM_INSTANCES : integer := data_width_a;
	
begin

gen_rams:
for i in 0 to NUM_RAM_INSTANCES-1 generate

inst_dpram_1w1r2c_ra: entity work.dpram_1w1r2c_ra
	GENERIC MAP 
	(
		addr_width	=>	addr_width_a,
		data_width	=>	1
	)
	PORT MAP 
	(
		clk_a	=>	clk_a,
		clk_b	=>	clk_b,
		en_a	=>	'1',
		en_b	=>	en_b,
		we_a	=>	we_a,
		addr_a	=>	addr_a,
		addr_b	=>	addr_b,
		din_a	=>	din_a(i downto i),
		dout_b	=>	dout_b(i downto i)
	);

end generate;

end Behavioral;