--------------------------------------------------------------------------
-- Project: JIPS, a portable 32-bit RISC CPU written in VHDL
-- This file: On-Chip work registers
--
-- Copyright (C) 2008 J. Ahrensfeld
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program.  If not, see <http://www.gnu.org/licenses/>.
--
-- For questions and ideas, please contact the author at jens@jayfield.org
--
--------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;

use work.mips_types.all;

entity dpram_1w1r1wc is
	Generic
	(
		addr_width : integer := 3;
		data_width : integer := 8
	);
	Port
	(
		clk_w		: in  STD_LOGIC;
		we			: in  STD_LOGIC;
		wptr		: in  unsigned (addr_width-1 downto 0);
		rptr		: in  unsigned (addr_width-1 downto 0);
		din			: in  unsigned (data_width-1 downto 0);
		dout		: out unsigned (data_width-1 downto 0)
	);
end dpram_1w1r1wc;

architecture Behavioral of dpram_1w1r1wc is

	constant depth : integer := 2**addr_width;
	type mem_t is array (0 to depth-1) of unsigned (data_width-1 downto 0);

	signal mem : mem_t;
	
begin

reg_in:
	process(clk_w)
	begin
		if rising_edge(clk_w) then
			if we = '1' then
				mem(to_integer(wptr)) <= din;
			end if;
		end if;	
	end process;

	dout <= mem(to_integer(rptr));

end Behavioral;