# ----------------------------------------------------------------------
# Project: JCPU, a portable 8-bit RISC CPU written in VHDL
# This file: The ROM file for upload to target over JTAG 

# Copyright (C) 2007 J. Ahrensfeld

# This library is free software; you can redistribute it and/or
# modify it under the terms of the GNU Lesser General Public
# License as published by the Free Software Foundation; either
# version 2.1 of the License, or (at your option) any later version.

# This library is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
# Lesser General Public License for more details.

# You should have received a copy of the GNU Lesser General Public
# License along with this library; if not, write to the Free Software
# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA

# For questions and ideas, please contact the author at jens@jayfield.org

# ---------------------------------------------------------------------

# Source JTAG/TCL frame work
#cd $env(CHIPSCOPE)\bin\nt
cd F:\\Xilinx9\\ChipScope_Pro_9_1i\\bin\\nt
source csejtag.tcl

namespace import ::chipscope::*

# Platform USB Cable
set PLATFORM_USB_CABLE_ARGS [list "port=USB2" \
                                  "frequency=6000000"]
                                  # frequency="24000000 | 12000000 | 6000000 | 3000000 | 1500000 | 750000"

set CABLE_NAME $CSEJTAG_TARGET_PLATFORMUSB                                  
set CABLE_ARGS $PLATFORM_USB_CABLE_ARGS

# Create session
set handle [::chipscope::csejtag_session create 0]

# Open JTAG and lock
set open_result [::chipscope::csejtag_target open $handle $CABLE_NAME 0 $CABLE_ARGS]
set lock_result [::chipscope::csejtag_target lock $handle 1000]

set devlist [::chipscope::csejtag_tap autodetect_chain $handle $CSEJTAG_SCAN_DEFAULT]

# Get Device ID
set devtype "Virtex-4SX"
set devid 2

# ---------------------------------------------------------------
# Shift the USER1 Instruction (b1111000010) into the Instruction Register of FPGA
# User 1
::chipscope::csejtag_tap shift_chain_ir $handle $CSEJTAG_SHIFT_READWRITE $CSEJTAG_RUN_TEST_IDLE 0 10 3C2

# Write Program
# JASM_ROM_INSERT_HERE

::chipscope::csejtag_target unlock $handle
::chipscope::csejtag_target close $handle
::chipscope::csejtag_session destroy $handle
exit