------------------------------------------------------------------------- -- Project: JCPU, a portable 8-bit RISC CPU written in VHDL -- This file: testbench for system test using Xilinx ML-402 -- Copyright (C) 2007 J. Ahrensfeld -- This library is free software; you can redistribute it and/or -- modify it under the terms of the GNU Lesser General Public -- License as published by the Free Software Foundation; either -- version 2.1 of the License, or (at your option) any later version. -- This library is distributed in the hope that it will be useful, -- but WITHOUT ANY WARRANTY; without even the implied warranty of -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU -- Lesser General Public License for more details. -- You should have received a copy of the GNU Lesser General Public -- License along with this library; if not, write to the Free Software -- Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA -- For questions and ideas, please contact the author at jens@jayfield.org ----------------------------------------------------------------------- LIBRARY ieee; use IEEE.STD_LOGIC_1164.ALL; USE ieee.numeric_std.ALL; use work.vga_types.all; ENTITY tb_vga_frontend64 IS END tb_vga_frontend64; ARCHITECTURE behavior OF tb_vga_frontend64 IS constant tsvga : vga_timespec_t := ts_vga_testbench; constant CLK_PERIOD : time := 10 ns; constant VGA_CLK_PERIOD : time := (integer(1E9) / tsvga.f_pxl_clk) * 1 ns; signal CLK_O : std_logic := '1'; signal RST_O : std_logic := '1'; -- Master signal INT_O : std_logic; signal CYC_O : std_logic; signal STB_O : std_logic; signal WE_O : std_logic; signal SEL_O : unsigned(3 downto 0) := (others => '1'); signal ACK_I : std_logic := '0'; signal MRDY_O : std_logic := '1'; signal SRDY_I : std_logic := '0'; signal ADDR_O : unsigned(31 downto 0) := (others => '-'); signal MDAT_I : unsigned(63 downto 0) := (others => '-'); signal MDAT_O : unsigned(63 downto 0) := (others => '-'); -- Slave signal CYC_I : std_logic := '0'; signal STB_I : std_logic := '0'; signal WE_I : std_logic := '0'; signal SEL_I : unsigned(7 downto 0); signal ACK_O : std_logic; signal MRDY_I : std_logic; signal SRDY_O : std_logic; signal ADDR_I : unsigned(31 downto 0) := (others => '0'); signal SDAT_I : unsigned(31 downto 0) := (others => '-'); signal SDAT_O : unsigned(31 downto 0) := (others => '-'); signal rdy : std_logic := '0'; signal read_reg : unsigned(31 downto 0) := (others => '-'); signal const_color : unsigned(31 downto 0) := X"0000_0000"; -- VGA signals signal vga_clk : std_logic := '1'; signal vga_red : unsigned(7 downto 0); signal vga_green : unsigned(7 downto 0); signal vga_blue : unsigned(7 downto 0); signal vga_blank_n : std_logic; signal vga_sync_n : std_logic; signal vga_hsync : std_logic; signal vga_vsync : std_logic; signal vga_en : std_logic; type blit_size_array_t is array (0 to 9) of natural; constant blit_size_x : blit_size_array_t := (8, 1, 2, 7, 8, 7, 1, 8, 8, 0); constant blit_size_y : blit_size_array_t := (8, 1, 2, 8, 7, 7, 8, 1, 0, 8); signal blit_count_rst : std_logic := '0'; type state_t is (IDLE, LA_SA, LA_SU, LU_SA, LU_SU, CC_SA, CC_SU); signal state : state_t := IDLE; type ram_t is array (0 to 127) of unsigned(63 downto 0); signal ram_src : ram_t := ( X"B000_0000_A000_0000", X"B000_0001_A000_0001", X"B000_0002_A000_0002", X"B000_0003_A000_0003", X"B000_0004_A000_0004", X"B000_0005_A000_0005", X"B000_0006_A000_0006", X"B000_0007_A000_0007", X"B000_0008_A000_0008", X"B000_0009_A000_0009", X"B000_000A_A000_000A", X"B000_000B_A000_000B", X"B000_000C_A000_000C", X"B000_000D_A000_000D", X"B000_000E_A000_000E", X"B000_000F_A000_000F", X"B000_0010_A000_0010", X"B000_0011_A000_0011", X"B000_0012_A000_0012", X"B000_0013_A000_0013", X"B000_0014_A000_0014", X"B000_0015_A000_0015", X"B000_0016_A000_0016", X"B000_0017_A000_0017", X"B000_0018_A000_0018", X"B000_0019_A000_0019", X"B000_001A_A000_001A", X"B000_001B_A000_001B", X"B000_001C_A000_001C", X"B000_001D_A000_001D", X"B000_001E_A000_001E", X"B000_001F_A000_001F", X"B000_0020_A000_0020", X"B000_0021_A000_0021", X"B000_0022_A000_0022", X"B000_0023_A000_0023", X"B000_0024_A000_0024", X"B000_0025_A000_0025", X"B000_0026_A000_0026", X"B000_0027_A000_0027", X"B000_0028_A000_0028", X"B000_0029_A000_0029", X"B000_002A_A000_002A", X"B000_002B_A000_002B", X"B000_002C_A000_002C", X"B000_002D_A000_002D", X"B000_002E_A000_002E", X"B000_002F_A000_002F", X"B000_0030_A000_0030", X"B000_0031_A000_0031", X"B000_0032_A000_0032", X"B000_0033_A000_0033", X"B000_0034_A000_0034", X"B000_0035_A000_0035", X"B000_0036_A000_0036", X"B000_0037_A000_0037", X"B000_0038_A000_0038", X"B000_0039_A000_0039", X"B000_003A_A000_003A", X"B000_003B_A000_003B", X"B000_003C_A000_003C", X"B000_003D_A000_003D", X"B000_003E_A000_003E", X"B000_003F_A000_003F", X"B000_0040_A000_0040", X"B000_0041_A000_0041", X"B000_0042_A000_0042", X"B000_0043_A000_0043", X"B000_0044_A000_0044", X"B000_0045_A000_0045", X"B000_0046_A000_0046", X"B000_0047_A000_0047", X"B000_0048_A000_0048", X"B000_0049_A000_0049", X"B000_004A_A000_004A", X"B000_004B_A000_004B", X"B000_004C_A000_004C", X"B000_004D_A000_004D", X"B000_004E_A000_004E", X"B000_004F_A000_004F", X"B000_0050_A000_0050", X"B000_0051_A000_0051", X"B000_0052_A000_0052", X"B000_0053_A000_0053", X"B000_0054_A000_0054", X"B000_0055_A000_0055", X"B000_0056_A000_0056", X"B000_0057_A000_0057", X"B000_0058_A000_0058", X"B000_0059_A000_0059", X"B000_005A_A000_005A", X"B000_005B_A000_005B", X"B000_005C_A000_005C", X"B000_005D_A000_005D", X"B000_005E_A000_005E", X"B000_005F_A000_005F", X"B000_0060_A000_0060", X"B000_0061_A000_0061", X"B000_0062_A000_0062", X"B000_0063_A000_0063", X"B000_0064_A000_0064", X"B000_0065_A000_0065", X"B000_0066_A000_0066", X"B000_0067_A000_0067", X"B000_0068_A000_0068", X"B000_0069_A000_0069", X"B000_006A_A000_006A", X"B000_006B_A000_006B", X"B000_006C_A000_006C", X"B000_006D_A000_006D", X"B000_006E_A000_006E", X"B000_006F_A000_006F", X"B000_0070_A000_0070", X"B000_0071_A000_0071", X"B000_0072_A000_0072", X"B000_0073_A000_0073", X"B000_0074_A000_0074", X"B000_0075_A000_0075", X"B000_0076_A000_0076", X"B000_0077_A000_0077", X"B000_0078_A000_0078", X"B000_0079_A000_0079", X"B000_007A_A000_007A", X"B000_007B_A000_007B", X"B000_007C_A000_007C", X"B000_007D_A000_007D", X"B000_007E_A000_007E", X"B000_007F_A000_007F" ); signal ram_dst : ram_t := ( X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000", X"0000_0000_0000_0000" ); BEGIN inst_vga_frontend64 : entity work.vga_frontend64 GENERIC MAP ( fifo_depth => 64, fifo_almost_full_thresh => 48, fifo_almost_empty_thresh => 16, BLIT_CHUNK_SIZE => 16, tsvga => tsvga ) PORT MAP ( -- System signals RST_I => RST_O, CLK_I => CLK_O, -- JBUS Master signals CYC_O => CYC_I, STB_O => STB_I, WE_O => WE_I, SEL_O => SEL_I, ACK_I => ACK_O, SRDY_I => SRDY_O, MRDY_O => MRDY_I, ADDR_O => ADDR_I, MDAT_I => MDAT_O, MDAT_O => MDAT_I, -- JBUS Slave signals INT_O => INT_O, CYC_I => CYC_O, STB_I => STB_O, WE_I => WE_O, SEL_I => SEL_O, ACK_O => ACK_I, SRDY_O => SRDY_I, MRDY_I => MRDY_O, ADDR_I => ADDR_O, SDAT_I => SDAT_O, SDAT_O => SDAT_I, -- VGA signals vga_clk_in => vga_clk, vga_clk_ce => vga_en, vga_red => vga_red, vga_green => vga_green, vga_blue => vga_blue, vga_blank_n => vga_blank_n, vga_sync_n => vga_sync_n, vga_hsync => vga_hsync, vga_vsync => vga_vsync ); vga_en <= not RST_O; rdy_GEN: process begin wait for 3*CLK_PERIOD/2; wait until rising_edge(CLK_O); rdy <= not rdy; end process; CLK_GEN: process begin wait for CLK_PERIOD/2; CLK_O <= not CLK_O; end process; VGA_CLK_GEN: process begin wait for VGA_CLK_PERIOD/2; vga_clk <= not vga_clk after 3 ns; end process; -- Slave SRDY_O <= CYC_I and rdy; process(CLK_O) variable ack_v : unsigned(11 downto 0); type arr64_t is array (11 downto 0) of unsigned(63 downto 0); variable dat_v : arr64_t; variable res: unsigned(63 downto 0); variable scan_count: unsigned(31 downto 0); variable ram_data : unsigned(63 downto 0); begin if rising_edge(CLK_O) then if RST_O = '1' then scan_count := X"00000000"; for i in 0 to 11 loop dat_v(i) := X"FFFFFFFF_FFFFFFFF"; ack_v(i) := '0'; end loop; else if (CYC_I and STB_I) = '1' and rdy = '1' then if WE_I = '0' then if ADDR_I(30) = '1' then if ADDR_I(2) = '0' then res := ADDR_I & scan_count; else res := scan_count & ADDR_I; end if; scan_count := scan_count + 8; else ram_data := ram_src(to_integer(ADDR_I(31 downto 3))); if ADDR_I(2) = '0' then res := ram_data; else res := ram_data(31 downto 0) & ram_data(63 downto 32); end if; end if; dat_v := dat_v(10 downto 0) & res; ack_v := ack_v(10 downto 0) & '1'; else -- WE=1 ram_data := ram_dst(to_integer(ADDR_I(31 downto 3))); ram_data := (others => '-'); if ADDR_I(2) = '0' then if SEL_I = "11111111" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I; elsif SEL_I = "00001111" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(31 downto 0); elsif SEL_I = "11110000" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(63 downto 32) & ram_data(31 downto 0); end if; else if SEL_I = "11111111" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & MDAT_I(63 downto 32); elsif SEL_I = "00001111" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= MDAT_I(31 downto 0) & ram_data(31 downto 0); elsif SEL_I = "11110000" then ram_dst(to_integer(ADDR_I(31 downto 3))) <= ram_data(63 downto 32) & MDAT_I(63 downto 32); end if; end if; end if; else dat_v := dat_v(10 downto 0) & X"FFFFFFFF_FFFFFFFF"; ack_v := ack_v(10 downto 0) & '0'; end if; MDAT_O <= dat_v(dat_v'left); ACK_O <= ack_v(ack_v'left); end if; end if; end process; process(CLK_O) begin if rising_edge(CLK_O) then if RST_O = '1' then read_reg <= X"00000000"; elsif ACK_I = '1' then read_reg <= SDAT_I; end if; end if; end process; -- Master STIMULUS: process variable result : unsigned(31 downto 0); procedure reg_write(reg, val : unsigned) is begin CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; WE_O <= '1'; ADDR_O <= reg; SDAT_O <= val; STB_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; CYC_O <= '0'; end procedure reg_write; procedure reg_read(reg : unsigned) is begin CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; WE_O <= '0'; ADDR_O <= reg; STB_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; wait until rising_edge(CLK_O) and ACK_I = '1'; result := SDAT_I; CYC_O <= '0'; end procedure reg_read; begin wait for 6*CLK_PERIOD; RST_O <= '0'; wait for 60*CLK_PERIOD; reg_write(X"0000_0018", X"4000_0000"); -- set frontbuffer address reg_write(X"0000_001C", X"4000_0000"); -- set backbuffer address reg_write(X"0000_0020", X"0000_0000"); -- set BLIT source address 0 reg_write(X"0000_0024", X"0000_0000"); -- set BLIT source dimension 0 reg_write(X"0000_0030", X"0000_0000"); -- set BLIT source address 1 reg_write(X"0000_0034", X"0000_0000"); -- set BLIT source dimension 1 reg_write(X"0000_0040", X"0000_0000"); -- set BLIT destination address reg_write(X"0000_0044", X"0000_0000"); -- set BLIT destination dimension -- Enable master reg_write(X"0000_0000", X"0000_0002"); -- Read status CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0000"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read resolution CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0014"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor X CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0008"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor Y CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_000C"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Write char 1 wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '1'; SDAT_O <= X"0000_0035"; ADDR_O <= X"0000_0004"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read char 1 wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0004"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Write char 2 wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '1'; SDAT_O <= X"0000_0045"; ADDR_O <= X"0000_0004"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read char 2 wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0004"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor X CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0008"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor Y CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_000C"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Set Cursor X wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '1'; SDAT_O <= X"0000_0012"; ADDR_O <= X"0000_0008"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Set Cursor Y wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '1'; SDAT_O <= X"0000_0014"; ADDR_O <= X"0000_000C"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor X CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_0008"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; -- Read Cursor Y CYC_O <= '1'; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '1'; WE_O <= '0'; ADDR_O <= X"0000_000C"; wait until rising_edge(CLK_O) and SRDY_I = '1'; STB_O <= '0'; wait until rising_edge(CLK_O); CYC_O <= '0'; wait for 60000*CLK_PERIOD; for i in 0 to blit_size_array_t'length-1 loop -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT aligned => aligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; state <= LA_SA; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; -- set source start address reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0000"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT unaligned => aligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; state <= LU_SA; -- set source start address reg_write(X"0000_0020", X"0000_0004"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0000"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT aligned => unaligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; state <= LA_SU; -- set source start address reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0004"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT unaligned => unaligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; state <= LU_SU; -- set source start address reg_write(X"0000_0020", X"0000_0004"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0004"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", (result and not X"0001_0000") or X"0000_0100"); -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT const => aligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; state <= CC_SA; const_color <= const_color + X"1111_1111"; -- set source start address reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0000"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", result or X"0001_0100"); -- wait for 600*CLK_PERIOD; ------------------------------------------------- -- BLIT const => unaligned test ------------------------------------------------- while(true) loop reg_read(X"0000_0000"); if result(8) = '0' then exit; end if; end loop; blit_count_rst <= '1'; wait until rising_edge(CLK_O); blit_count_rst <= '0'; state <= CC_SU; const_color <= const_color + X"1111_1111"; -- set source start address reg_write(X"0000_0020", X"0000_0000"); -- set src dim-x reg_write(X"0000_0024", to_unsigned(32, 32)); -- set destination start address reg_write(X"0000_0040", X"0000_0004"); -- set constant color reg_write(X"0000_0058", const_color); -- set dst dim-x reg_write(X"0000_0044", to_unsigned(32, 32)); -- set nx reg_write(X"0000_0050", to_unsigned(blit_size_x(i), 32)); -- set ny reg_write(X"0000_0054", to_unsigned(blit_size_y(i), 32)); -- set blit request reg_read(X"0000_0000"); reg_write(X"0000_0000", result or X"0001_0100"); -- wait for 600*CLK_PERIOD; end loop; state <= IDLE; wait; end process; END;